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UPSTREAM: mainboard/google/reef: indicate dual rank LPDDR4 skus

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The 16Gb devices use two ranks per channel within the DRAM module.
However, the density settings are really on a per rank basis so
indicate dual rank with a device density of 8Gb.

BUG=chrome-os-partner:55446

Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15772
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362689
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Aaron Durbin 2016-07-21 10:00:39 -05:00 • committed by chrome-bot
parent d7a92a5f9d
commit 8f89b7c50d
1 changed files with 19 additions and 7 deletions
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26
src/mainboard/google/reef/romstage.c
View file

@ -71,11 +71,17 @@ static const struct lpddr4_swizzle_cfg board_swizzle = {
#define PROTO_SKU 15
static const struct lpddr4_sku skus[] = {
/* K4F6E304HB-MGCJ - both logical channels */
/*
* K4F6E304HB-MGCJ - both logical channels While the parts
* are listed at 16Gb there are 2 ranks per channel so indicate
* the deneisty as 8Gb per rank.
*/
[0] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_16Gb_DENSITY,
.ch1_density = LP4_16Gb_DENSITY,
.ch0_density = LP4_8Gb_DENSITY,
.ch1_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
},
/* K4F8E304HB-MGCJ - both logical channels */
[1] = {
@ -83,13 +89,19 @@ static const struct lpddr4_sku skus[] = {
.ch0_density = LP4_8Gb_DENSITY,
.ch1_density = LP4_8Gb_DENSITY,
},
/* MT53B512M32D2NP-062WT:C - both logical channels */
/*
* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
* are listed at 16Gb there are 2 ranks per channel so indicate
* the deneisty as 8Gb per rank.
*/
[2] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_16Gb_DENSITY,
.ch1_density = LP4_16Gb_DENSITY,
/* MT53B256M32D1NP-062 WT:C - both logical channels */
.ch0_density = LP4_8Gb_DENSITY,
.ch1_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
},
/* MT53B256M32D1NP-062 WT:C - both logical channels */
[3] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_8Gb_DENSITY,