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UPSTREAM: mainboard/google/reef: apply EVT board changes

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Based on the board revision apply the correct GPIO changes.
The only differences are the addition of 2 peripheral wake signals
and a dedicated peripheral reset line.

BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961
BRANCH=None
TEST=Built and tested on reef.

BUG=None
BRANCH=None
TEST=None

Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Original-Reviewed-on: https://review.coreboot.org/15562
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358897
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Aaron Durbin 2016-07-06 23:16:01 -05:00 • committed by chrome-bot
parent 8268395641
commit 8dc56e1ce6
2 changed files with 28 additions and 3 deletions
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16
src/mainboard/google/reef/gpio.h
View file

@ -274,7 +274,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_0, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_1, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_2, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_3, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_4, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_5, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_6, UP_20K, DEEP),
@ -287,7 +286,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */
PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_APIC(GPIO_18, NONE, DEEP, LEVEL, NONE), /* Trackpad IRQ */
@ -319,7 +317,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */
PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */
PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */
@ -356,5 +353,18 @@ static const struct pad_config early_gpio_table[] = {
#define MEM_CONFIG1 GPIO_102
#define MEM_CONFIG0 GPIO_101
static const struct pad_config proto_diff_table[] = {
PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */
PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */
};
/* Wake peripheral signals post proto. */
static const struct pad_config nonproto_diff_table[] = {
PAD_CFG_GPI_SCI(GPIO_3, UP_20K, DEEP, LEVEL, NONE), /* FP_INT_L */
PAD_CFG_GPI_SCI(GPIO_15, NONE, DEEP, LEVEL, NONE), /* TRACKPAD_INT_1V8_ODL */
PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */
};
#endif /* __ACPI__ */
#endif /* MAINBOARD_GPIO_H */

15
src/mainboard/google/reef/mainboard.c
View file

@ -14,6 +14,7 @@
*/
#include <arch/acpi.h>
#include <boardid.h>
#include <console/console.h>
#include <device/device.h>
#include <nhlt.h>
@ -24,7 +25,21 @@
static void mainboard_init(void *chip_info)
{
int boardid;
boardid = board_id();
printk(BIOS_INFO, "Board ID: %d\n", boardid);
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
/* Apply proto board settings if board matches. */
if (boardid == 0)
gpio_configure_pads(proto_diff_table,
ARRAY_SIZE(proto_diff_table));
else
gpio_configure_pads(nonproto_diff_table,
ARRAY_SIZE(nonproto_diff_table));
mainboard_ec_init();
}