mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Fixed to no longer used old chip/intel/serial_subr.c
added serial_subr.c to lib setup_serial.inc is for sis
This commit is contained in:
Ronald G. Minnich
parent
b28409f2ce
commit
8d7c3938b0
7 changed files with 405 additions and 3 deletions
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@ -121,7 +121,7 @@ mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/chip/intel/serial_subr.c
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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@ -123,7 +123,7 @@ mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/chip/intel/serial_subr.c
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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@ -124,7 +124,7 @@ mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/chip/intel/serial_subr.c
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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168
romimages/WINFAST6300_SERCONS/Makefile
Normal file
168
romimages/WINFAST6300_SERCONS/Makefile
Normal file
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@ -0,0 +1,168 @@
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CPUFLAGS=-DSIS630 -Di386 -Di486 -Di686 -Di586 -D__KERNEL__
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CPUFLAGS += -DINTEL_BRIDGE_CONFIG -DSIS630_NVRAM
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CPUFLAGS += -DINTEL_PPRO_MTRR -DSIS630_KEYBOARD
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# CPUFLAGS += -DMUST_ENABLE_FLOPPY
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CPUFLAGS += -DSIS_FIXUP_FOR_FB
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CPUFLAGS += -DHAVE_FRAMEBUFFER
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
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CPUFLAGS += -DINBUF_COPY
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CPUFLAGS += -DUSE_DOC_MIL
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "'
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CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
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LINUX=$(TOP)/../linux-2.4.0-test6.sis
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TOP=../..
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INCLUDES=-nostdinc -I $(TOP)/src/include
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CFLAGS=$(INCLUDES) -O2 $(CPUFLAGS) -Ilinux/include -Wall
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OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o
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OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o
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OBJECTS += southbridge.o northbridge.o superio.o
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#OBJECTS += pci.o
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OBJECTS += printk.o vsprintf.o
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OBJECTS += newpci.o linuxpci.o
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OBJECTS += cpuid.o
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OBJECTS += irq_tables.o
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OBJECTS += serial_subr.o
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OBJECTS += mpspec.o
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OBJECTS += microcode.o
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OBJECTS += keyboard.o
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LINK = ld -T ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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all: romimage
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floppy: all
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mcopy -o romimage a:
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# here's the problem: we shouldn't assume we come up with more than
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# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
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# enable all flash and then gunzip the linuxbios. As a result,
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block docipl
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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cp romimage /tmp
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docipl: ipl.o
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objcopy -O binary -R .note -R .comment -S ipl.o docipl
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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linuxbios.strip: linuxbios
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objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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linuxbios: $(OBJECTS) vmlinux.bin.gz
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@rm -f biosobject
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$(LINK)
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nm -n linuxbios > linuxbios.map
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# crt0 actually includes .inc files.
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# For self-documenting purposes, we put the FULL PATH of the
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# .inc files (relative to $TOP/src) in crt0.S.
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# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc
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# To make this work, add the extra -I $(TOP)/src here.
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crt0.s: $(TOP)/src/mainboard/leadtek/winfast6300/crt0.S
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$(CCASM) -I $(TOP)/src -E $< > crt0.s
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crt0.o : crt0.s
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$(CCASM) -c crt0.s
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mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
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cc $(CFLAGS) -c $<
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mainboard.o: $(TOP)/src/mainboard/leadtek/winfast6300/mainboard.c
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cc $(CFLAGS) -c $<
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fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
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cc $(CFLAGS) -c $<
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params.o: $(TOP)/src/lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
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cc $(CFLAGS) -c $<
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southbridge.o: $(TOP)/src/northsouthbridge/sis/630/southbridge.c
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cc $(CFLAGS) -c $<
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northbridge.o: $(TOP)/src/northsouthbridge/sis/630/northbridge.c
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cc $(CFLAGS) -c $<
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superio.o: $(TOP)/src/superio/sis/950/superio.c
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cc $(CFLAGS) -c $<
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pci.o: $(TOP)/src/lib/pci.c
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cc $(CFLAGS) -c $<
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irq_tables.o: $(TOP)/src/mainboard/leadtek/winfast6300/irq_tables.c
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cc $(CFLAGS) -o $@ -c $<
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mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
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cc $(CFLAGS) -c $<
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subr.o: $(TOP)/src/lib/subr.c
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cc $(CFLAGS) -c $<
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keyboard.o: $(TOP)/src/pc80/keyboard.c
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cc $(CFLAGS) -c $<
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cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
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cc $(CFLAGS) -c $<
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mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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$(CC) $(CFLAGS) -c $<
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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cc $(CFLAGS) -c $<
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vsprintf.o: $(TOP)/src/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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newpci.o: $(TOP)/src/lib/newpci.c
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cc $(CFLAGS) -c $<
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linuxpci.o: $(TOP)/src/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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ipl.o: $(TOP)/src/northsouthbridge/sis/630/ipl.S
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gcc -c -I$(TOP)/northsouthbridge/sis/630 $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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vmlinux.bin.gz: vmlinux.bin
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gzip -f -3 vmlinux.bin
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vmlinux.bin: $(LINUX)/vmlinux
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objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
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alltags:
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gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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clean::
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rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
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rm -f a.out *.s *.l
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rm -f TAGS tags
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rm -f docipl
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114
romimages/WINFAST6300_SERCONS/ldscript.ld
Normal file
114
romimages/WINFAST6300_SERCONS/ldscript.ld
Normal file
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@ -0,0 +1,114 @@
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*
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* $Id$
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*
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*/
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/* oh, barf. This won't work if all you use is .o's. -- RGM */
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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* Memory map:
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*
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* 0x00000 (4*4096 bytes) : stack
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* 0x04000 (4096 bytes) : private data
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* 0x05000 : data space
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* 0x90000 : kernel stack
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* 0xf0000 (64 Kbyte) : EPROM
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*/
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MEMORY
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{
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ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is max for STPC */
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rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
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}
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_PDATABASE = 0x04000;
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_RAMBASE = 0x05000;
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_KERNSTK = 0x90000;
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/* should be parameterized but is not, yuck! */
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_ROMBASE = 0x80000;
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/*
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* Entry point is not really nececary, since the mkrom(8)
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* tool creates a entry point that jumps to $0xc000:0x0000.
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*/
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/* baloney, but ... RGM*/
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ENTRY(_start)
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SECTIONS
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{
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text _ROMBASE : {
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_text = .;
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*(.text);
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*(.rodata);
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_etext = .;
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}
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_pdata = .;
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/*
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.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
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SIZEOF(.rodata)) {
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*/
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.pdata _PDATABASE : AT ( _etext ) {
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*(.pdata);
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}
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_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
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_data = .;
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*(.data)
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*(.sdata)
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*(.sdata2)
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*(.got)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between __bss_start and __bss_end with zeroes.
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*/
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.bss ( ADDR(.data) + SIZEOF(.data) ) : {
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_bss = .;
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*(.bss)
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*(.sbss)
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*(COMMON)
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_ebss = .;
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_heap = .;
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}
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}
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/*
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* This provides the start and end address for the whole image
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*/
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_image = LOADADDR(.text);
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_eimage = LOADADDR(.data) + SIZEOF(.data);
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/* EOF */
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77
src/lib/serial_subr.c
Normal file
77
src/lib/serial_subr.c
Normal file
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@ -0,0 +1,77 @@
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#include <cpu/p5/io.h>
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#include "serial_subr.h"
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/* Base Address */
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#define TTYS0 0x3f8
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/* Data */
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#define TTYS0_RBR (TTYS0+0x00)
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/* Control */
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#define TTYS0_TBR TTYS0_RBR
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#define TTYS0_IER (TTYS0+0x01)
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#define TTYS0_IIR (TTYS0+0x02)
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#define TTYS0_FCR TTYS0_IIR
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#define TTYS0_LCR (TTYS0+0x03)
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#define TTYS0_MCR (TTYS0+0x04)
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#define TTYS0_DLL TTYS0_RBR
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#define TTYS0_DLM TTYS0_IER
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/* Status */
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#define TTYS0_LSR (TTYS0+0x05)
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#define TTYS0_MSR (TTYS0+0x06)
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#define TTYS0_SCR (TTYS0+0x07)
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void ttys0_tx_char(char data) {
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while (!(inb(TTYS0_LSR) & 0x20));
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outb(data, TTYS0_TBR);
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}
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void ttys0_tx_string(char *data) {
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while (*data) {
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if (*data=='\n') ttys0_tx_char('\r');
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ttys0_tx_char(*data++);
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}
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}
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void ttys0_tx_hex_digit(char data) {
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data &= 0x0f;
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if (data>9) {
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data += ('a'-10);
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}
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else {
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data += '0';
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}
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ttys0_tx_char(data);
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}
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void ttys0_tx_hex(unsigned int data, int digits) {
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int ii;
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/* ttys0_tx_string("0x"); */
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for (ii = 0; ii<digits; ii++) {
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ttys0_tx_hex_digit((char)(data >> ((digits - ii - 1)*4)));
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}
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}
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void ttys0_tx_int(int data) {
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int ii, i2;
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int digit[30];
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ii = 0;
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do {
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digit[ii] = data % 10;
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data = data/10;
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} while ((ii++ < 30) && data);
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for (i2=0; i2<ii; i2++) {
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ttys0_tx_hex_digit((char)digit[ii-i2-1]);
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}
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}
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43
src/superio/sis/950/setup_serial.inc
Normal file
43
src/superio/sis/950/setup_serial.inc
Normal file
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@ -0,0 +1,43 @@
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#define OUTIT(val, port) movb val, %al; \
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outb %al, port
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#define OUT2E(val) OUTIT(val, $0x2e)
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#define OUT2F(val) OUTIT(val, $0x2f)
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/* to do: move this to a common include file! */
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#define WRITESIOBYTE(register, value) movw register, %dx ;\
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movb value, %al ;\
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outb %al, %dx
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#define WRITESIOWORD(register, value) movw register, %dx ;\
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movw value, %ax ;\
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outw %ax, %dx
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/* turn on PnP */
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OUT2E($0x87)
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OUT2E($1)
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OUT2E($0x55)
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OUT2E($0x55)
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/* select com1 */
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OUT2E($7)
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OUT2F($1)
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/* set the enable in reg. 0x30 */
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OUT2E($0x30)
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OUT2F($1)
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/* turn off PnP */
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OUT2E($2)
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OUT2F($2)
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/* all done that nonsense -- from here on it's standard pc80 */
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// set up register to set baud rate.
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WRITESIOBYTE($0x3fb, $0x80)
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// Set 115 kb
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WRITESIOWORD($0x3f8, $1)
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// Set 9.6 kb
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// WRITESIOWORD($0x3f8, $12)
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// now set no parity, one stop, 8 bits
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WRITESIOBYTE($0x3fb, $3)
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// now turn on RTS, DRT
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WRITESIOBYTE($0x3fc, $3)
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// Enable interrupts
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WRITESIOBYTE($0x3f9, $0xf)
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// should be done. Dump a char for fun.
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WRITESIOBYTE($0x3f8, $48)
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Loading…
Add table
Reference in a new issue