From 888063b4af0bc6c5cf8be0839864015cb3e135c0 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Fri, 4 Jan 2008 23:19:49 +0000 Subject: [PATCH] These changes implement a fixed Geode LX Cache As Ram that allows a return from disable_car. - Move the cache as ram memory to 0x80000 instead of 0xc8000, as the C range is really tricky to get right :-) - Modify the geode disable_car to ensure the cache is flushed to ram on the wbinvd. With these changes, I get a payload loaded. Signed-off-by: Ronald G. Minnich Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@546 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- arch/x86/geodelx/stage1.c | 10 +++++++++- include/arch/x86/amd_geodelx.h | 7 ++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/x86/geodelx/stage1.c b/arch/x86/geodelx/stage1.c index f5c26bc6a5..d3130b47e7 100644 --- a/arch/x86/geodelx/stage1.c +++ b/arch/x86/geodelx/stage1.c @@ -22,6 +22,7 @@ #include #include #include +#include static const struct msrinit msr_table[] = { /* Setup access to cache under 1MB. */ @@ -59,5 +60,12 @@ void disable_car(void) for (i = 0; i < ARRAY_SIZE(msr_table); i++) wrmsr(msr_table[i].msrnum, msr_table[i].msr); - __asm__("wbinvd\n"); + /* OK, here is the theory: we should be able to copy + * the data back over itself, and the wbinvd should then + * flush to memory. Let's see. + */ + __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); + __asm__ __volatile__ ("wbinvd\n"); + banner(BIOS_DEBUG, "Disable_car: done wbinvd"); + banner(BIOS_DEBUG, "disable_car: done"); } diff --git a/include/arch/x86/amd_geodelx.h b/include/arch/x86/amd_geodelx.h index 7941659404..e3bacd6fb4 100644 --- a/include/arch/x86/amd_geodelx.h +++ b/include/arch/x86/amd_geodelx.h @@ -566,7 +566,12 @@ /* ------------------------ */ #define DCACHE_RAM_SIZE 0x08000 -#define DCACHE_RAM_BASE 0xc8000 +#define DCACHE_RAM_BASE 0x80000 +/* This is where the DCache will be mapped and be used as stack. It would be + * cool if it was the same base as LinuxBIOS normal stack. + */ +#define LX_STACK_BASE DCACHE_RAM_BASE +#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) /* This is where the DCache will be mapped and be used as stack. It would be * cool if it was the same base as LinuxBIOS normal stack. */