From 87301c39bda4bb5fd1ef1135a0a063831f3e9e29 Mon Sep 17 00:00:00 2001
From: Abhay Kumar <abhay.kumar@intel.com>
Date: Thu, 14 Jul 2016 18:43:54 -0700
Subject: [PATCH] UPSTREAM: soc/intel/apollolake: Remove PEIM GFX from normal
 mode and S3 resume

Do not pass VBT table to fsp in normal mode and S3 resume so that
PEIM GFX will not get initialized.

BUG=None
BRANCH=None
TEST=None

Change-Id: I78e3241b15d385292f5c22c74f2fc1ad23890531
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/365323
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/apollolake/chip.c |  3 +--
 src/soc/intel/common/vbt.c      | 20 ++++++++++++++++++++
 src/soc/intel/common/vbt.h      |  5 +++++
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 544cd133c8..10b71fbc8d 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -194,8 +194,7 @@ static void soc_init(void *data)
 	struct global_nvs_t *gnvs;
 
 	/* Save VBT info and mapping */
-	if (locate_vbt(&vbt_rdev) != CB_ERR)
-		vbt = rdev_mmap_full(&vbt_rdev);
+	vbt = vbt_get(&vbt_rdev);
 
 	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
 	 * default policy that doesn't honor boards' requirements. */
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index 80b17a2f87..d9bb98a8d1 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -15,6 +15,8 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <arch/acpi.h>
+#include <bootmode.h>
 
 #include "vbt.h"
 
@@ -40,3 +42,21 @@ enum cb_err locate_vbt(struct region_device *rdev)
 
 	return CB_SUCCESS;
 }
+
+void *vbt_get(struct region_device *rdev)
+{
+	void *vbt_data;
+
+	/* Normal mode and S3 resume path PEIM GFX init is not needed.
+	 * Passing NULL as VBT will not make PEIM GFX to execute. */
+	if (acpi_is_wakeup_s3())
+		return NULL;
+	if (!display_init_required())
+		return NULL;
+	if (locate_vbt(rdev) != CB_ERR) {
+		vbt_data = rdev_mmap_full(rdev);
+		return vbt_data;
+	} else {
+		return NULL;
+	}
+}
diff --git a/src/soc/intel/common/vbt.h b/src/soc/intel/common/vbt.h
index e1a45cc887..9a02e6a467 100644
--- a/src/soc/intel/common/vbt.h
+++ b/src/soc/intel/common/vbt.h
@@ -21,4 +21,9 @@
 
 /* locate .vbt file */
 enum cb_err locate_vbt(struct region_device *rdev);
+/*
+ * Returns VBT pointer and mapping after checking prerequisites for Pre OS
+ * Graphics initialization
+ */
+void *vbt_get(struct region_device *rdev);
 #endif