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Two remaining issues:

Browse source 
/home/rminnich/coreboot-v3/build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: dual_channel_slew_group_lookup.3242 single_channel_slew_group_lookup.3243

and
/home/rminnich/coreboot-v3/southbridge/intel/i82801gx/smbus.c:34: error: conflicting types for ‘smbus_read_byte’
include/device/smbus.h:56: error: previous declaration of ‘smbus_read_byte’ was here

we are working these. The second is much harder than it seems. 
It concerns whether we put i2c devices (i.e. DRAM spd SEEPROMS) in the dts.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1026 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-11-14 17:14:16 +00:00
parent dd5e033e5f
commit 863bcbff3b
5 changed files with 20 additions and 5 deletions
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2
mainboard/kontron/986lcd-m/cmos.layout
View file

@ -129,6 +129,6 @@ enumerations
# -----------------------------------------------------------------
checksums
checksum 392 983 984
#checksum 392 983 984

1
mainboard/kontron/986lcd-m/initram.c
View file

@ -212,4 +212,5 @@ int main(void)
}
#endif
MCHBAR16(SSKPD) = 0xCAFE;
return 0;
}

11
mainboard/kontron/986lcd-m/mainboard.h
View file

@ -20,3 +20,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define CHANNEL_XOR_RANDOMIZATION 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 1
/* never defined in v2 */
#define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID 0
#define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID 0
/* nowhere else to go yet */
#define TEST_SMM_FLASH_LOCKDOWN 0
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL 1

10
southbridge/intel/i82801gx/lpc.c
View file

@ -28,6 +28,8 @@
#include <io.h>
#include <statictree.h>
#include <config.h>
#include <mainboard.h>
#include <mc146818rtc.h>
#include "i82801gx.h"
#include "../../../northbridge/intel/i945/ich7.h"
@ -159,10 +161,10 @@ static void i82801gx_power_options(struct device * dev)
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
printk_info ("NMI sources enabled.\n");
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */
} else {
printk_info ("NMI sources disabled.\n");
printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
}
outb(reg8, 0x70);
@ -181,7 +183,6 @@ static void i82801gx_power_options(struct device * dev)
void i82801gx_rtc_init(struct device *dev)
{
u8 reg8;
u32 reg32;
int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
@ -218,8 +219,9 @@ static void enable_hpet(struct device *dev)
static void i82801gx_lock_smm(struct device *dev)
{
void smm_lock(void);
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
#endif
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode

1
southbridge/intel/i82801gx/pci.c
View file

@ -27,6 +27,7 @@
#include <device/pci_ids.h>
#include <statictree.h>
#include <config.h>
#include <mainboard.h>
static void pci_init(struct device *dev)
{