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UPSTREAM: gm45: enable setting all vram sizes from cmos
Setting the size of the preallocated memory for the igd is done
using a cmos parameter, gfx_uma_size. This was limited to a subset of
all available sizes, that were already implemented elsewhere
in the northbridge code.
What this does is change the cmos parameter to 4 bits instead
of 3 bits to accomodate all vram sizes.
It also adds a sane default of 32mb that already was in place.
The northbridge code that reads this cmos parameter is
also changed for this new cmos settings.
352M is disabled since it causes issues on systems with 4GB or more ram.
TEST: Build, flash target. Clear cmos by corrupting
the checksum (nvramtool -c something).
Set a desired value in gfx_uma_size using nvramtool.
"dmesg | grep stolen" to see what is actually allocated.
Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/14900
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
(cherry-picked from commit 7afcfe0f9f)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350083
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Arthur Heymans
chrome-bot
parent
7c9d804f50
commit
83bcd9a358
6 changed files with 49 additions and 28 deletions
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@ -13,4 +13,5 @@ sticky_fn=Disable
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power_management_beeps=Enable
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low_battery_beep=Enable
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sata_mode=AHCI
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hybrid_graphics_mode=Integrated Only
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hybrid_graphics_mode=Integrated Only
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gfx_uma_size=32M
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@ -77,8 +77,8 @@ entries
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940 1 e 1 uwb
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# coreboot config options: northbridge
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941 3 e 11 gfx_uma_size
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944 2 e 12 hybrid_graphics_mode
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946 4 e 11 gfx_uma_size
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# coreboot config options: EC
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952 8 h 0 volume
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@ -127,12 +127,18 @@ enumerations
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9 1 Primary
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10 0 AHCI
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10 1 Compatible
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11 0 32M
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11 1 48M
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11 2 64M
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11 3 128M
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11 5 96M
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11 6 160M
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11 0 1M
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11 1 4M
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11 2 8M
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11 3 16M
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11 4 32M
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11 5 48M
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11 6 64M
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11 7 128M
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11 8 256M
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11 9 96M
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11 10 160M
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11 11 224M
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12 0 Integrated Only
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12 1 Discrete Only
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@ -13,3 +13,4 @@ sticky_fn=Disable
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power_management_beeps=Enable
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low_battery_beep=Enable
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sata_mode=AHCI
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gfx_uma_size=32M
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@ -77,9 +77,8 @@ entries
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940 1 e 1 uwb
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# coreboot config options: northbridge
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941 3 e 11 gfx_uma_size
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944 8 h 0 volume
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952 4 e 11 gfx_uma_size
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# coreboot config options: check sums
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984 16 h 0 check_sum
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@ -125,12 +124,18 @@ enumerations
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9 1 Primary
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10 0 AHCI
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10 1 Compatible
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11 0 32M
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11 1 48M
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11 2 64M
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11 3 128M
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11 5 96M
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11 6 160M
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11 0 1M
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11 1 4M
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11 2 8M
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11 3 16M
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11 4 32M
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11 5 48M
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11 6 64M
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11 7 128M
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11 8 256M
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11 9 96M
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11 10 160M
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11 11 224M
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# -----------------------------------------------------------------
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checksums
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@ -70,9 +70,9 @@ entries
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984 16 h 0 check_sum
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# coreboot config options: northbridge
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1000 3 e 10 gfx_uma_size
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1000 4 e 10 gfx_uma_size
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#1003 21 r 0 unused
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#1004 20 r 0 unused
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# ram initialization internal data
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1024 128 r 0 read_training_results
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@ -112,13 +112,18 @@ enumerations
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8 1 Yes
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9 0 AHCI
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9 1 Compatible
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10 0 32M
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10 1 48M
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10 2 64M
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10 3 128M
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10 5 96M
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10 6 160M
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11 0 1M
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11 1 4M
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11 2 8M
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11 3 16M
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11 4 32M
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11 5 48M
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11 6 64M
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11 7 128M
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11 8 256M
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11 9 96M
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11 10 160M
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11 11 224M
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# -----------------------------------------------------------------
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checksums
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@ -153,10 +153,13 @@ void igd_compute_ggc(sysinfo_t *const sysinfo)
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/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
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2MB GTT + 2MB shadow GTT (0x0b00) else. */
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if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
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/* 0 for 32MB */
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gfxsize = 0;
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/* 4 for 32MB, default if not set in cmos */
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gfxsize = 4;
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}
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sysinfo->ggc = 0x0300 | ((gfxsize + 5) << 4);
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/* Handle invalid cmos settings */
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if (gfxsize > 11)
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gfxsize = 4;
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sysinfo->ggc = 0x0300 | ((gfxsize + 1) << 4);
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if (!(capid & (1 << (48 - 32))))
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sysinfo->ggc |= 0x0800;
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}
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