From 81f842a04827adde43af59648c123f026e702f82 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 25 Jul 2016 14:44:51 -0700
Subject: [PATCH] UPSTREAM: soc/intel/apollolake: Disable monitor mwait

The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around

BUG=chrome-os-partner:55110
BRANCH=None
TEST=None

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Reviewed-on: https://chromium-review.googlesource.com/363939
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/soc/intel/apollolake/chip.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index c71e59a26c..544cd133c8 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -394,6 +394,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 
 	silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
 
+	/* Disable monitor mwait since it is broken due to a hardware bug without a fix */
+	silconfig->MonitorMwaitEnable = 0;
+
 	/* Disable setting of EISS bit in FSP. */
 	silconfig->SpiEiss = 0;
 }