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This patch fixes whitespace so that my next patch is easier to read.

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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles


git-svn-id: svn://coreboot.org/repository/coreboot-v3@952 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2008-10-24 17:53:03 +00:00
parent 9b90a6f22b
commit 7e654ac7a0
2 changed files with 101 additions and 99 deletions
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165
northbridge/amd/k8/common.c
View file

@ -76,6 +76,7 @@ void debug_fx_devs(void)
} }
} }
#endif #endif
void get_fx_devs(void) void get_fx_devs(void)
{ {
int i; int i;
@ -123,48 +124,48 @@ struct hw_mem_hole_info get_hw_mem_hole_info(void)
struct hw_mem_hole_info mem_hole; struct hw_mem_hole_info mem_hole;
int i; int i;
mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1; mem_hole.node_id = -1;
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
u32 base; u32 base;
u32 hole; u32 hole;
base = f1_read_config32(0x40 + (i << 3)); base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue; continue;
}
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
mem_hole.node_id = i; // record the node No with hole
break; // only one hole
} }
}
//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk hole = pci_read_config32(__f1_dev[i], 0xf0);
if(mem_hole.node_id==-1) { if(hole & 1) { // we find the hole
u32 limitk_pri = 0; mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
for(i=0; i<8; i++) { mem_hole.node_id = i; // record the node No with hole
u32 base, limit; break; // only one hole
unsigned base_k, limit_k; }
base = f1_read_config32(0x40 + (i << 3)); }
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base_k = (base & 0xffff0000) >> 2; //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
if(limitk_pri != base_k) { // we find the hole if(mem_hole.node_id==-1) {
mem_hole.hole_startk = limitk_pri; u32 limitk_pri = 0;
mem_hole.node_id = i; for(i=0; i<8; i++) {
break; //only one hole u32 base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
} }
limit = f1_read_config32(0x44 + (i << 3)); base_k = (base & 0xffff0000) >> 2;
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; if(limitk_pri != base_k) { // we find the hole
limitk_pri = limit_k; mem_hole.hole_startk = limitk_pri;
} mem_hole.node_id = i;
} break; //only one hole
}
limit = f1_read_config32(0x44 + (i << 3));
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
limitk_pri = limit_k;
}
}
return mem_hole; return mem_hole;
@ -172,35 +173,35 @@ struct hw_mem_hole_info get_hw_mem_hole_info(void)
void disable_hoist_memory(unsigned long hole_startk, int i) void disable_hoist_memory(unsigned long hole_startk, int i)
{ {
int ii; int ii;
struct device * dev; struct device * dev;
u32 base, limit; u32 base, limit;
u32 hoist; u32 hoist;
u32 hole_sizek; u32 hole_sizek;
//1. find which node has hole //1. find which node has hole
//2. change limit in that node. //2. change limit in that node.
//3. change base and limit in later node //3. change base and limit in later node
//4. clear that node f0 //4. clear that node f0
//if there is not mem hole enabled, we need to change it's base instead //if there is not mem hole enabled, we need to change it's base instead
hole_sizek = (4*1024*1024) - hole_startk; hole_sizek = (4*1024*1024) - hole_startk;
for(ii=7;ii>i;ii--) { for(ii=7;ii>i;ii--) {
base = f1_read_config32(0x40 + (ii << 3)); base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue; continue;
} }
limit = f1_read_config32(0x44 + (ii << 3)); limit = f1_read_config32(0x44 + (ii << 3));
f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
} }
limit = f1_read_config32(0x44 + (i << 3)); limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
dev = __f1_dev[i]; dev = __f1_dev[i];
hoist = pci_read_config32(dev, 0xf0); hoist = pci_read_config32(dev, 0xf0);
if(hoist & 1) { if(hoist & 1) {
pci_write_config32(dev, 0xf0, 0); pci_write_config32(dev, 0xf0, 0);
@ -214,30 +215,30 @@ void disable_hoist_memory(unsigned long hole_startk, int i)
u32 hoist_memory(unsigned long hole_startk, int i) u32 hoist_memory(unsigned long hole_startk, int i)
{ {
int ii; int ii;
u32 carry_over; u32 carry_over;
struct device * dev; struct device * dev;
u32 base, limit; u32 base, limit;
u32 basek; u32 basek;
u32 hoist; u32 hoist;
carry_over = (4*1024*1024) - hole_startk; carry_over = (4*1024*1024) - hole_startk;
for(ii=7;ii>i;ii--) { for(ii=7;ii>i;ii--) {
base = f1_read_config32(0x40 + (ii << 3)); base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue; continue;
} }
limit = f1_read_config32(0x44 + (ii << 3)); limit = f1_read_config32(0x44 + (ii << 3));
f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
} }
limit = f1_read_config32(0x44 + (i << 3)); limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
dev = __f1_dev[i]; dev = __f1_dev[i];
base = pci_read_config32(dev, 0x40 + (i << 3)); base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2; basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) { if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow //don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024 //so need to change base reg instead, new basek will be 4*1024*1024
@ -247,17 +248,17 @@ u32 hoist_memory(unsigned long hole_startk, int i)
} }
else else
{ {
hoist = /* hole start address */ hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) + ((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */ /* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) + (((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */ /* enable */
1; 1;
pci_write_config32(dev, 0xf0, hoist); pci_write_config32(dev, 0xf0, hoist);
} }
return carry_over; return carry_over;
} }
#endif #endif

35
northbridge/amd/k8/domain.c
View file

@ -126,18 +126,18 @@ static void k8_pci_domain_read_resources(struct device * dev)
} }
} }
#ifndef CONFIG_PCI_64BIT_PREF_MEM #ifndef CONFIG_PCI_64BIT_PREF_MEM
/* Initialize the system wide io space constraints */ /* Initialize the system-wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400; resource->base = 0x400;
resource->limit = 0xffffUL; resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */ /* Initialize the system-wide memory resource constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
#else #else
/* Initialize the system wide io space constraints */ /* Initialize the system-wide io space constraints */
resource = new_resource(dev, 0); resource = new_resource(dev, 0);
resource->base = 0x400; resource->base = 0x400;
resource->limit = 0xffffUL; resource->limit = 0xffffUL;
@ -145,7 +145,7 @@ static void k8_pci_domain_read_resources(struct device * dev)
compute_allocate_resource(&dev->link[0], resource, compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO); IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide prefetchable memory resources constraints */ /* Initialize the system-wide prefetchable memory resource constraints */
resource = new_resource(dev, 1); resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
@ -153,7 +153,7 @@ static void k8_pci_domain_read_resources(struct device * dev)
IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH); IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system wide memory resources constraints */ /* Initialize the system-wide memory resource constraints */
resource = new_resource(dev, 2); resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM; resource->flags = IORESOURCE_MEM;
@ -197,10 +197,10 @@ static void k8_pci_domain_set_resources(struct device * dev)
mem2 = find_resource(dev, 2); mem2 = find_resource(dev, 2);
#if 1 #if 1
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align); mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align); mem2->base, mem2->limit, mem2->size, mem2->align);
#endif #endif
/* See if both resources have roughly the same limits */ /* See if both resources have roughly the same limits */
@ -227,10 +227,10 @@ static void k8_pci_domain_set_resources(struct device * dev)
} }
#if 1 #if 1
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align); mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align); mem2->base, mem2->limit, mem2->size, mem2->align);
#endif #endif
last = &dev->resource[dev->resources]; last = &dev->resource[dev->resources];
@ -264,10 +264,11 @@ static void k8_pci_domain_set_resources(struct device * dev)
#endif #endif
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek /* If the hw mem hole is already set in raminit stage, here we will
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * compare mmio_basek and hole_basek. If mmio_basek is bigger than
* otherwise We reset the hole to the mmio_basek * hole_basek, we use hole_basek as mmio_basek and we don't need
*/ * to reset hole. Otherwise, we reset the hole to the mmio_basek.
*/
mem_hole = get_hw_mem_hole_info(); mem_hole = get_hw_mem_hole_info();