Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: amd/pi/hudson: Add SERIRQ setup

Browse source 
Enable SERIRQ in quiet or continuous mode based on Kconfig.
Defaults to quite mode.

BUG=none
BRANCH=none
TEST=none

Change-Id: I1f479d87f10a1fdac21b71de106e07673d89c92b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3eec9dda1f
Original-Change-Id: Ib40a84719fcc3a5d6b3000c3c0412f1bcf629609
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19234
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480109
This commit is contained in:
Marc Jones 2017-04-09 18:00:40 -06:00 • committed by chrome-bot
parent a95d893abf
commit 79f1beb99f
2 changed files with 13 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/southbridge/amd/pi/hudson/Kconfig
View file

@ -213,6 +213,12 @@ config AMDFW_OUTSIDE_CBFS
option to manually attach the generated amdfw.rom at an
offset of 0x20000 from the bottom of the coreboot ROM image.
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
endif
config HUDSON_UART

7
src/southbridge/amd/pi/hudson/lpc.c
View file

@ -83,6 +83,13 @@ static void lpc_init(device_t dev)
/* Initialize i8254 timers */
setup_i8254 ();
/* Setup SERIRQ, enable continuous mode */
byte = (BIT(4) | BIT(7));
if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
byte |= BIT(6);
pm_write8(PM_SERIRQ_CONF, byte);
}
static void hudson_lpc_read_resources(device_t dev)