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UPSTREAM: mainboard/google/reef: support WLAN_PE_RST
The reef DVT build added another way to assert the wifi module's reset line. Ensure it's deasserted by default. For previous boards this GPIO doesn't matter because it wasn't routed anyway. BUG=chrome-os-partner:56737 BRANCH=None TEST=None Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677 Reviewed-on: https://chromium-review.googlesource.com/380993 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1 changed files with 4 additions and 1 deletions
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@ -271,7 +271,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */
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PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */
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PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */
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PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */
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PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */
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PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */
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PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* SIO_SPI_2_RXD */
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/* WLAN_PE_RST - default to deasserted. */
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PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */
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PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */
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PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */
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/* Debug tracing. */
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/* Debug tracing. */
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@ -348,6 +349,8 @@ static const struct pad_config early_gpio_table[] = {
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/* I2C2 - TPM */
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/* I2C2 - TPM */
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PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
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PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
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PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
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PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
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/* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
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PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */
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};
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};
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/* GPIO settings before entering sleep. */
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/* GPIO settings before entering sleep. */
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