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Various smaller code fixes:

Browse source 
- Use 'static' for functions and structs which are not meant to be public.

 - Use 'const' for variables which are not meant to be modified.

 - Move some prototypes into legacy.h where they belong.

 - Drop prototypes for non-existing functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@460 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-07-20 14:03:39 +00:00
parent 064cd70619
commit 7705f6a682
11 changed files with 61 additions and 77 deletions
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2
arch/x86/geodelx/cpu.c
View file

@ -83,7 +83,7 @@ static void lx_init(struct device *dev)
* in multiple CPU files and use the device ID, at scan time, to pick which
* one is used. There is a lot of flexibility here!
*/
struct device_operations geodelx_cpuops = {
static struct device_operations geodelx_cpuops = {
.constructor = default_device_constructor,
.phase3_scan = NULL,
.phase6_init = lx_init,

8
arch/x86/geodelx/geodelx.c
View file

@ -55,7 +55,7 @@
* Timer 1 was used for RAM refresh on XT/AT and can be read on port 61.
* Port 61 is used by many timing loops for calibration.
*/
void start_timer1(void)
static void start_timer1(void)
{
outb(0x56, I82C54_CONTROL_WORD_REGISTER);
outb(0x12, I82C54_COUNTER1);
@ -122,7 +122,7 @@ static void disable_memory_reorder(void)
*
* For CPU version C3. Should be the only released version.
*/
void cpu_bug(void)
static void cpu_bug(void)
{
pci_deadlock();
disable_memory_reorder();
@ -258,7 +258,7 @@ u32 pci_speed(void)
/**
* Delay Control Settings table from AMD (MCP 0x4C00000F).
*/
const struct delay_controls {
static const struct delay_controls {
u8 dimms;
u8 devices;
u32 slow_hi;
@ -306,7 +306,7 @@ const struct delay_controls {
* @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
* @param dimm1 The SMBus address of DIMM 1 (mainboard dependent).
*/
void set_delay_control(u8 dimm0, u8 dimm1)
static void set_delay_control(u8 dimm0, u8 dimm1)
{
u32 msrnum, glspeed;
u8 spdbyte0, spdbyte1, dimms, i;

2
arch/x86/geodelx/stage1.c
View file

@ -23,7 +23,7 @@
#include <msr.h>
#include <amd_geodelx.h>
static struct msrinit {
static const struct msrinit {
u32 msrnum;
struct msr msr;
} msr_table[] = {

7
include/arch/x86/cpu.h
View file

@ -196,11 +196,4 @@ static inline __attribute__((always_inline)) void hlt(void)
__asm__ __volatile__("hlt" : : : "memory");
}
/* Random other functions. These are not architecture-specific, except they
* really are in many ways. Seperate the PC from the "X86" is hard.
*/
void uart_init(void);
void rtc_init(int invalid);
void isa_dma_init(void);
#endif /* ARCH_X86_CPU_H */

5
include/arch/x86/legacy.h
View file

@ -32,3 +32,8 @@
#define I82C54_COUNTER0 0x40
#define I82C54_COUNTER1 0x41
#define I82C54_COUNTER2 0x42
void setup_i8259(void);
void uart_init(void);
void rtc_init(int invalid);
void isa_dma_init(void);

37
northbridge/amd/geodelx/geodelx.c
View file

@ -26,6 +26,12 @@
#include <msr.h>
#include <amd_geodelx.h>
/* Function prototypes */
extern void chipsetinit(void);
extern u32 get_systop(void);
extern void northbridge_init_early(void);
extern void setup_realmode_idt(void);
/* Here is programming for the various MSRs. */
#define IM_QWAIT 0x100000
@ -93,19 +99,9 @@
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
/* TODO: Should be in some header file? */
extern void graphics_init(void);
extern void cpu_bug(void);
extern void chipsetinit(void);
extern void print_conf(void);
extern u32 get_systop(void);
void northbridge_init_early(void);
void setup_realmode_idt(void);
void do_vsmbios(void);
struct msr_defaults {
int msr_no;
/* TODO: Not used!? */
static const struct msr_defaults {
u32 msr_no;
struct msr msr;
} msr_defaults[] = {
{ 0x1700, {.hi = 0,.lo = IM_QWAIT}},
@ -221,10 +217,11 @@ static void geodelx_northbridge_init(struct device *dev)
msr.hi |= 0x3;
msr.lo |= 0x30000;
printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n",
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
MSR_GLIU0_SHADOW, msr.hi, msr.lo);
printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n",
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
MSR_GLIU1_SHADOW, msr.hi, msr.lo);
/* TODO: Is the respective wrmsr() missing? */
#endif
}
@ -234,7 +231,7 @@ static void geodelx_northbridge_init(struct device *dev)
*
* @param dev The nortbridge device.
*/
void geodelx_northbridge_set_resources(struct device *dev)
static void geodelx_northbridge_set_resources(struct device *dev)
{
struct resource *resource, *last;
unsigned int link;
@ -376,8 +373,6 @@ static void geodelx_pci_domain_phase2(struct device *dev)
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
northbridge_init_early();
#warning cpu bug has been moved to initram stage
/* cpu_bug(); */
chipsetinit();
setup_realmode_idt();
@ -435,7 +430,7 @@ static void cpu_bus_noop(struct device *dev)
*/
/** Operations for when the northbridge is running a PCI domain. */
struct device_operations geodelx_pcidomain_ops = {
static struct device_operations geodelx_pcidomain_ops = {
.constructor = default_device_constructor,
.phase2_setup_scan_bus = geodelx_pci_domain_phase2,
.phase3_scan = geodelx_pci_domain_scan_bus,
@ -447,7 +442,7 @@ struct device_operations geodelx_pcidomain_ops = {
};
/** Operations for when the northbridge is running an APIC cluster. */
struct device_operations geodelx_apic_ops = {
static struct device_operations geodelx_apic_ops = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = cpu_bus_noop,
@ -458,7 +453,7 @@ struct device_operations geodelx_apic_ops = {
};
/** Operations for when the northbridge is running a PCI device. */
struct device_operations geodelx_pci_ops = {
static struct device_operations geodelx_pci_ops = {
.constructor = default_device_constructor,
.phase3_scan = geodelx_pci_domain_scan_bus,
.phase4_read_resources = geodelx_pci_domain_read_resources,

10
northbridge/amd/geodelx/geodelxinit.c
View file

@ -31,7 +31,7 @@ struct gliutable {
unsigned long hi, lo;
};
struct gliutable gliu0table[] = {
static struct gliutable gliu0table[] = {
/* 0-7FFFF to MC */
{.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,
.lo = 0x0FFF80},
@ -54,7 +54,7 @@ struct gliutable gliu0table[] = {
{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
};
struct gliutable gliu1table[] = {
static struct gliutable gliu1table[] = {
/* 0-7FFFF to MC */
{.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,
.lo = 0x0FFF80},
@ -78,14 +78,14 @@ struct gliutable gliu1table[] = {
{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
};
struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
static struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
struct msrinit {
unsigned long msrnum;
struct msr msr;
};
struct msrinit clock_gating_default[] = {
static struct msrinit clock_gating_default[] = {
{GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
{MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
{VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
@ -101,7 +101,7 @@ struct msrinit clock_gating_default[] = {
};
/** GeodeLink priority table. */
struct msrinit geode_link_priority_table[] = {
static struct msrinit geode_link_priority_table[] = {
{CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}},
{DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}},
{VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}},

4
northbridge/amd/geodelx/raminit.c
View file

@ -196,7 +196,7 @@ static void check_ddr_max(u8 dimm0, u8 dimm1)
}
}
const u16 REFRESH_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
static const u16 REFRESH_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
/**
* Compute a refresh rate.
@ -238,7 +238,7 @@ static void set_refresh_rate(u8 dimm0, u8 dimm1)
}
/* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
const u8 CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 };
static const u8 CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 };
/**
* Compute the CAS rate.

42
southbridge/amd/cs5536/cs5536.c
View file

@ -24,20 +24,18 @@
#include <device/pci.h>
#include <msr.h>
#include <amd_geodelx.h>
#include <cpu.h> // TODO: Move rtc_init() etc. to legacy.h
#include <legacy.h>
#include <device/pci_ids.h>
#include <statictree.h>
#include "cs5536.h"
extern void setup_i8259(void);
struct msrinit {
u32 msrnum;
struct msr msr;
};
/* Master configuration register for bus masters */
struct msrinit SB_MASTER_CONF_TABLE[] = {
static struct msrinit SB_MASTER_CONF_TABLE[] = {
{USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
{ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}},
{AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
@ -46,33 +44,33 @@ struct msrinit SB_MASTER_CONF_TABLE[] = {
};
/* CS5536 clock gating */
struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
static struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
{GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
{GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
{GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
{MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
{MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
{ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
{AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
{0, {0, 0}}
};
struct acpiinit {
struct acpi_init {
u16 ioreg;
u32 regdata;
};
struct acpiinit acpi_init_table[] = {
{ACPI_IO_BASE + 0x00, 0x01000000},
{ACPI_IO_BASE + 0x08, 0x00000000},
{ACPI_IO_BASE + 0x0C, 0x00000000},
{ACPI_IO_BASE + 0x1C, 0x00000000},
{ACPI_IO_BASE + 0x18, 0xFFFFFFFF},
{ACPI_IO_BASE + 0x00, 0x0000FFFF},
{PMS_IO_BASE + PM_SCLK, 0x000000E00},
{PMS_IO_BASE + PM_SED, 0x000004601},
{PMS_IO_BASE + PM_SIDD, 0x000008C02},
{PMS_IO_BASE + PM_WKD, 0x0000000A0},
{PMS_IO_BASE + PM_WKXD, 0x0000000A0},
static const struct acpi_init acpi_init_table[] = {
{ACPI_IO_BASE + 0x00, 0x01000000},
{ACPI_IO_BASE + 0x08, 0x00000000},
{ACPI_IO_BASE + 0x0C, 0x00000000},
{ACPI_IO_BASE + 0x1C, 0x00000000},
{ACPI_IO_BASE + 0x18, 0xFFFFFFFF},
{ACPI_IO_BASE + 0x00, 0x0000FFFF},
{PMS_IO_BASE + PM_SCLK, 0x00000E00},
{PMS_IO_BASE + PM_SED, 0x00004601},
{PMS_IO_BASE + PM_SIDD, 0x00008C02},
{PMS_IO_BASE + PM_WKD, 0x000000A0},
{PMS_IO_BASE + PM_WKXD, 0x000000A0},
{0, 0}
};
@ -82,14 +80,14 @@ struct FLASH_DEVICE {
unsigned long fMask; /* Flash size/mask */
};
struct FLASH_DEVICE FlashInitTable[] = {
static const struct FLASH_DEVICE FlashInitTable[] = {
{FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */
{FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */
{FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */
{FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */
};
u32 FlashPort[] = {
static const u32 FlashPort[] = {
MDD_LBAR_FLSH0,
MDD_LBAR_FLSH1,
MDD_LBAR_FLSH2,
@ -521,7 +519,7 @@ void chipsetinit(void)
#if 0
if (!IsS3Resume())
{
struct acpiinit *aci = acpi_init_table;
struct acpi_init *aci = acpi_init_table;
for (; aci->ioreg; aci++) {
outl(aci->regdata, aci->ioreg);
inl(aci->ioreg);

7
southbridge/amd/cs5536/cs5536.h
View file

@ -442,14 +442,7 @@
#define FLASH_IO_256B 0x0000FF00
/* Function prototypes */
void cs5536_setup_extmsr(void);
void cs5536_setup_idsel(void);
void cs5536_usb_swapsif(void);
void cs5536_setup_iobase(void);
void cs5536_setup_power_button(void);
void cs5536_setup_smbus_gpio(void);
void cs5536_disable_internal_uart(void);
void cs5536_setup_cis_mode(void);
void cs5536_setup_onchipuart(void);
void cs5536_stage1(void);

14
southbridge/amd/cs5536/stage1.c
View file

@ -38,7 +38,7 @@
* The routing is controlled by an MSR. This appears to be the same on
* all boards.
*/
void cs5536_setup_extmsr(void)
static void cs5536_setup_extmsr(void)
{
struct msr msr;
@ -61,7 +61,7 @@ void cs5536_setup_extmsr(void)
* Setup PCI IDSEL for CS5536. There is a Magic Register that must be
* written so that the chip appears at the expected place in the PCI tree.
*/
void cs5536_setup_idsel(void)
static void cs5536_setup_idsel(void)
{
/* Write IDSEL to the write once register at address 0x0000. */
outl(0x1 << (CS5536_DEV_NUM + 10), 0);
@ -72,7 +72,7 @@ void cs5536_setup_idsel(void)
* These are not the bits you're looking for. You can go about your business.
* Move along, move along.
*/
void cs5536_usb_swapsif(void)
static void cs5536_usb_swapsif(void)
{
struct msr msr;
@ -95,7 +95,7 @@ void cs5536_usb_swapsif(void)
* the resources are there as needed. The values are hardcoded because,
* this early in the process, fancy allocation can do more harm than good.
*/
void cs5536_setup_iobase(void)
static void cs5536_setup_iobase(void)
{
struct msr msr;
@ -134,7 +134,7 @@ void cs5536_setup_iobase(void)
*
* If GPIO24 is not enabled then soft-off will not work.
*/
void cs5536_setup_power_button(void)
static void cs5536_setup_power_button(void)
{
/* TODO: Should be a #define? */
outl(0x40020000, PMS_IO_BASE + 0x40);
@ -148,7 +148,7 @@ void cs5536_setup_power_button(void)
* An unknown question at this point is how general this is to all mainboards.
* At the same time, many boards seem to follow this particular reference spec.
*/
void cs5536_setup_smbus_gpio(void)
static void cs5536_setup_smbus_gpio(void)
{
u32 val;
@ -196,7 +196,7 @@ void cs5536_disable_internal_uart(void)
* the southbridge and the CPU chips. At the same time, they always seem
* to use mode B.
*/
void cs5536_setup_cis_mode(void)
static void cs5536_setup_cis_mode(void)
{
struct msr msr;