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mainboard/asus/kgpe-d16: Enable CC6

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Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11978
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Timothy Pearson 2015-06-05 21:14:23 -05:00 • committed by Ronald G. Minnich
parent cfb93e70bf
commit 74e03a4fdd
3 changed files with 12 additions and 2 deletions
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1
src/mainboard/asus/kgpe-d16/cmos.default
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@ -14,6 +14,7 @@ ecc_scrub_rate = 1.28us
interleave_chip_selects = Enable interleave_chip_selects = Enable
interleave_nodes = Disable interleave_nodes = Disable
interleave_memory_channels = Enable interleave_memory_channels = Enable
cpu_cc6_state = Enable
ieee1394_controller = Enable ieee1394_controller = Enable
power_on_after_fail = On power_on_after_fail = On
boot_option = Fallback boot_option = Fallback

3
src/mainboard/asus/kgpe-d16/cmos.layout
View file

@ -38,7 +38,8 @@ entries
458 4 e 11 hypertransport_speed_limit 458 4 e 11 hypertransport_speed_limit
462 2 e 12 minimum_memory_voltage 462 2 e 12 minimum_memory_voltage
464 1 e 2 compute_unit_siblings 464 1 e 2 compute_unit_siblings
465 1 r 0 allow_spd_nvram_cache_restore 465 1 e 1 cpu_cc6_state
466 1 r 0 allow_spd_nvram_cache_restore
477 1 e 1 ieee1394_controller 477 1 e 1 ieee1394_controller
728 256 h 0 user_data 728 256 h 0 user_data
984 16 h 0 check_sum 984 16 h 0 check_sum

10
src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
View file

@ -621,7 +621,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x124, data->f1x124); write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x124, data->f1x124);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x10c, data->f2x10c); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x10c, data->f2x10c);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x114, data->f2x114); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x114, data->f2x114);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); if (is_fam15h())
/* Do not set LockDramCfg or CC6SaveEn at this time */
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118 & ~(0x3 << 18));
else
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0);
write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44); write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44);
@ -1013,6 +1017,10 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* ECC scrub rate control */ /* ECC scrub rate control */
pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x58, data->f3x58); pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x58, data->f3x58);
if (is_fam15h())
/* Set LockDramCfg and CC6SaveEn */
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118);
} }
} }
} }