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Basic syntax errors and other compilation errors fixed. Now to shoot for

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link-time errors (e.g. udelay etc.)
This commit is contained in:
Ronald G. Minnich 2002-10-17 21:09:15 +00:00
parent 36a7dd48fc
commit 7377b062c9
8 changed files with 30 additions and 18 deletions
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1
src/arch/i386/lib/Config
View file

@ -4,3 +4,4 @@ object hardwaremain.o
object pirq_routing.o HAVE_PIRQ_TABLE
object vgabios.o CONFIG_VGABIOS
object idt.o CONFIG_REALMODE_IDT
option CONFIG_LOGICAL_CPUS=1

1
src/include/pci.h
View file

@ -425,6 +425,7 @@ extern void compute_allocate_resource(struct pci_dev *bus, struct resource *brid
unsigned long type_mask, unsigned long type);
extern void assign_resources(struct pci_dev *bus);
extern void enumerate_static_device(void);
extern unsigned long pci_memory_base;
#include <pciconf.h>
/* linkages from devices of a type (e.g. superio devices)

5
src/include/pci_ids.h
View file

@ -1229,13 +1229,14 @@
#define PCI_DEVICE_ID_INTEL_82801CA_1E0 0x244e
#define PCI_DEVICE_ID_INTEL_82801CA_1F0 0x2480
#define PCI_DEVICE_ID_INTEL_82801CA_1F1 0x248b
#define PCI_DEVICE_ID_INTEL_82801CA_1D2 0x2482
#define PCI_DEVICE_ID_INTEL_82801CA_1D0 0x2482
#define PCI_DEVICE_ID_INTEL_82801CA_1F3 0x2483
#define PCI_DEVICE_ID_INTEL_82801CA_1D1 0x2484
#define PCI_DEVICE_ID_INTEL_82801CA_1F5 0x2485
#define PCI_DEVICE_ID_INTEL_82801CA_1D2 0x2487
#define PCI_DEVICE_ID_INTEL_82870_1F0 0x1461
#define PCI_DEVICE_ID_INTEL_82870_1E0 0x1461
#define PCI_DEVICE_ID_INTEL_82870_1F0 0x1460
#define PCI_DEVICE_ID_INTEL_82820FW_0 0x2440
#define PCI_DEVICE_ID_INTEL_82820FW_1 0x2442

6
src/include/superio/w83627hf.h
View file

@ -44,6 +44,12 @@
#define KBC_DEFAULT_IOBASE1 0x64
#define KBC_DEFAULT_IRQ0 0x1
#define KBC_DEFAULT_IRQ1 0xc
#define HW_MONITOR_DEFAULT_IOBASE0 0x295
#define LED_OFF 0x00
#define LED_ON 0x40
#define LED_BLINK_1SEC 0x80
#define LED_BLINK_4SEC 0xC0
#if !defined(ASSEMBLY)
void w83627hf_enter_pnp(unsigned char port);

27
src/lib/newpci.c
View file

@ -31,6 +31,8 @@ static char rcsid[] = "$Id$";
*/
#define PCI_ALLOCATE_TIGHT 1
unsigned long pci_memory_base = 0xc0000000;
static const struct pci_ops *conf;
struct pci_ops {
@ -540,7 +542,7 @@ void compute_allocate_resource(
resource = 0;
/* Walk through all the devices on the current bus and compute the addresses */
while((dev = largest_resource(bus, &resource, type_mask, type))) {
while(dev = largest_resource(bus, &resource, type_mask, type)) {
unsigned long size;
/* Do NOT I repeat do not ignore resources which have zero size.
* If they need to be ignored dev->read_resources should not even
@ -775,6 +777,7 @@ void assign_resources(struct pci_dev *bus)
for (curdev = bus->children; curdev; curdev = curdev->sibling) {
curdev->ops->set_resources(curdev);
}
printk_debug("ASSIGNED RESOURCES, bus %d\n", bus->secondary);
}
static void enable_resources(struct pci_dev *bus)
@ -836,6 +839,7 @@ void pci_configure(void)
#else
root->resource[1].base = PCI_MEM_START;
#endif
pci_memory_base = root->resource[1].base;
root->resource[1].flags |= IORESOURCE_SET;
// now just set things into registers ... we hope ...
root->ops->set_resources(root);
@ -879,30 +883,29 @@ void pci_initialize(void)
void
handle_superio(int pass, struct superio *all_superio[], int nsuperio)
{
int i = 0;
struct superio *s = all_superio[0];
int i;
struct superio *s;
printk_debug("handle_superio start, s %p nsuperio %d s->super %p\n",
s, nsuperio, s->super);
printk_debug("handle_superio start, nsuperio %d\n", nsuperio);
for (; i < nsuperio; i++){
for (i = 0; i < nsuperio; i++){
s = all_superio[i];
printk_debug(__FUNCTION__
" Pass %d, check #%d, s %p s->super %p\n",
pass, i, s, s->super);
" Pass %d, check #%d, s %p s->super %p\n",
pass, i, s, s->super);
if (!s->super) {
printk_debug(__FUNCTION__
" Pass %d, Skipping #%d as it has no superio pointer!\n",
pass, i);
" Pass %d, Skipping #%d as it has no superio pointer!\n",
pass, i);
continue;
}
printk_debug("handle_superio: Pass %d, Superio %s\n",
pass, s->super->name);
pass, s->super->name);
// if no port is assigned use the defaultport
printk_info(__FUNCTION__ " port 0x%x, defaultport 0x%x\n",
s->port, s->super->defaultport);
s->port, s->super->defaultport);
if (!s->port)
s->port = s->super->defaultport;

2
src/northbridge/intel/E7500/northbridge.c
View file

@ -89,5 +89,5 @@ struct mem_range *sizeram(void)
mem[3].basek = 0;
mem[3].sizek = 0;
return &mem;
return (struct mem_range *) &mem;
}

4
src/southbridge/intel/82801ca/ich3_ioapic.c
View file

@ -9,8 +9,8 @@ void ich3_enable_ioapic(void)
{
struct pci_dev *dev;
u32 dword;
volatile u32 *ioapic_sba=0xfec00000;
volatile u32 *ioapic_sbd=0xfec00010;
volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000;
volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010;
dev = pci_find_device(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82801CA_1F0, 0);

2
src/southbridge/intel/82870/p64h2_ioapic.c
View file

@ -31,7 +31,7 @@ void p64h2_enable_ioapic(void)
}
/* Read the MBAR address for setting up the io apic in io memory space */
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &dword);
ioapic_a=dword;
ioapic_a = (u32 *) dword;
ioapic_d = ioapic_a +0x04;
printk_debug("IOAPIC %d at %02x:%02x.%01x MBAR = %x DataAddr = %x\n",
addr, dev->bus->secondary,