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UPSTREAM: mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indents

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16785
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: If6b36ebef49dd2733d272f990bb7c6623d4ab1b1
Reviewed-on: https://chromium-review.googlesource.com/391081
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Elyes HAOUAS 2016-09-28 21:41:06 +02:00 • committed by chrome-bot
parent a8b3a88f4f
commit 72e8d09cf1
1 changed files with 9 additions and 9 deletions
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18
src/mainboard/asus/kfsn4-dre_k8/romstage.c
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@ -299,11 +299,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); printk(BIOS_DEBUG, "ck804_early_setup_x()\n");
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
/* FIDVID change will issue one LDTSTOP and the HT change will be effective too */ /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */
if (needs_reset) { if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n"); printk(BIOS_INFO, "ht reset -\n");
soft_reset(); soft_reset();
} }
post_code(0x3b); post_code(0x3b);
@ -323,8 +323,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
* IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
*/ */
if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
dump_spd_registers(&cpu[0]); dump_spd_registers(&cpu[0]);
dump_smbus_registers(); dump_smbus_registers();
} }
#endif #endif
@ -348,8 +348,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Initialize GPIO */ /* Initialize GPIO */
/* Access SuperIO GPI03 logical device */ /* Access SuperIO GPI03 logical device */
uint16_t port = GPIO3_DEV >> 8; uint16_t port = GPIO3_DEV >> 8;
outb(0x87, port); outb(0x87, port);
outb(0x87, port); outb(0x87, port);
pnp_set_logical_device(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV);
/* Set GP37 (power LED) to output */ /* Set GP37 (power LED) to output */
pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); pnp_write_config(GPIO3_DEV, 0xf0, 0x7f);