Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs

Browse source 
Change-Id: Ic65f8d2cbb5bc459cf513c6b34a5f1846cb2b897
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6549
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Edward O'Callaghan 2014-08-09 15:48:51 +10:00
parent ff0df2bba5
commit 728ff392e7
1 changed files with 15 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
src/cpu/amd/geode_lx/cache_as_ram.inc
View file

@ -189,24 +189,25 @@ DCacheSetupGood:
call main call main
done_cache_as_ram_main: done_cache_as_ram_main:
/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ /* We now run over the stack-in-cache,
* copying it back to itself to invalidate the cache */
push %edi push %edi
mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
push %esi push %esi
mov $(CONFIG_DCACHE_RAM_BASE),%edi mov $(CONFIG_DCACHE_RAM_BASE),%edi
mov %edi,%esi mov %edi,%esi
cld cld
rep movsl %ds:(%esi),%es:(%edi) rep movsl %ds:(%esi),%es:(%edi)
pop %esi pop %esi
pop %edi pop %edi
/* Clear the cache out to ram */ /* Clear the cache out to ram */
wbinvd wbinvd
/* re-enable the cache */ /* re-enable the cache */
movl %cr0, %eax movl %cr0, %eax
xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
movl %eax, %cr0 movl %eax, %cr0
__main: __main:
post_code(POST_PREPARE_RAMSTAGE) post_code(POST_PREPARE_RAMSTAGE)
@ -227,4 +228,3 @@ __main:
post_code(POST_DEAD_CODE) post_code(POST_DEAD_CODE)
hlt hlt
jmp .Lhlt jmp .Lhlt