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UPSTREAM: google/rambi: disable PCI device for unused i2c buses
Light sensor isn't used and ACPI already removed, so disable
I2C5 bus interface as well.
Disable I2C6 for devices without a touchscreen
BUG=none
BRANCH=none
TEST=none
Change-Id: I82dd1cfe7fc9f5635391431dd00b7bd67b8b916a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f848ed091e
Original-Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19956
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523968
This commit is contained in:
parent
957b71ac5e
commit
72020b0141
11 changed files with 15 additions and 15 deletions
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@ -59,7 +59,7 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.5 off end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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@ -71,7 +71,7 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.5 off end # I2C5
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device pci 18.6 off end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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@ -68,7 +68,7 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.5 off end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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@ -71,8 +71,8 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.5 off end # I2C5
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device pci 18.6 off end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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device pci 1b.0 on end # HDA
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@ -71,7 +71,7 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.5 off end # I2C5
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device pci 18.6 off end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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@ -68,7 +68,7 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.5 off end # I2C5
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device pci 18.6 off end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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@ -72,7 +72,7 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.5 off end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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@ -68,7 +68,7 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.5 off end # I2C5
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device pci 18.6 off end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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@ -71,8 +71,8 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.5 off end # I2C5
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device pci 18.6 off end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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device pci 1b.0 on end # HDA
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