mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
430tx support (beginnings of)
This commit is contained in:
Ronald G. Minnich
parent
4dc5eb479e
commit
6f65f07fdf
3 changed files with 549 additions and 0 deletions
5
src/northbridge/intel/430tx/Config
Normal file
5
src/northbridge/intel/430tx/Config
Normal file
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@ -0,0 +1,5 @@
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raminit northbridge/intel/430tx/raminit.inc
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raminit sdram/generic_sdram.inc
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raminit sdram/generic_sdram_enable.inc
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object northbridge.o
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30
src/northbridge/intel/430tx/northbridge.c
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30
src/northbridge/intel/430tx/northbridge.c
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@ -0,0 +1,30 @@
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#include <pci.h>
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unsigned long sizeram()
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{
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/*
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* This is written for BX but should work also for GX.
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*/
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unsigned long totalmem;
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unsigned char banks;
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struct pci_dev *pcidev;
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/* pci_find_device is way overkill for the host bridge!
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* Plus the BX & GX have different device numbers so it
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* prevents code sharing.
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*/
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pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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pci_read_config_byte(pcidev, 0x67, &banks);
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totalmem = (unsigned long) banks *8 * 1024;
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if (banks == 0) {
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totalmem = 0x80000000UL;
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}
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return totalmem;
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}
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514
src/northbridge/intel/430tx/raminit.inc
Normal file
514
src/northbridge/intel/430tx/raminit.inc
Normal file
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@ -0,0 +1,514 @@
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jmp intel_430_out
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#define USE_SPD 1
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#define CS_WRITE_BYTE(addr, byte) \
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movl $addr, %eax ; \
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movl $byte, %edx ; \
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PCI_WRITE_CONFIG_BYTE
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#define CS_WRITE_WORD(addr, word) \
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movl $addr, %eax ; \
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movl $word, %ecx ; \
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PCI_WRITE_CONFIG_WORD
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#define CS_WRITE_LONG(addr, dword) \
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movl $addr, %eax ; \
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movl $dword, %ecx ; \
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PCI_WRITE_CONFIG_DWORD
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/* Default memory set to 0 */
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#define DRB 0x00
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/* The DRB register for the first row */
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#define DRB_REG0 $0x60
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/* The maximum allowed rows of memory banks */
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#define MAX_ROWS $0x8
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#define RAM_READ 0x0400
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#define DIMM0_BASE \
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xorl %eax, %eax
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#define DIMM_BASE(n) \
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movl $(0x60 + ((n) -1)), %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0xFF, %eax ; \
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shll $23, %eax ; \
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#define DIMM_READ \
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addl %ebx, %eax ; \
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movl (%eax), %edx ; \
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xorl $0xdff8, %eax ; \
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movl (%eax), %edx
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#define DIMM0_READ DIMM0_BASE ; DIMM_READ
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#define DIMM1_READ DIMM_BASE(1) ; DIMM_READ
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#define DIMM2_READ DIMM_BASE(2) ; DIMM_READ
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#define DIMM3_READ DIMM_BASE(3) ; DIMM_READ
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#define DIMM4_READ DIMM_BASE(4) ; DIMM_READ
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#define DIMM5_READ DIMM_BASE(5) ; DIMM_READ
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#define DIMM6_READ DIMM_BASE(6) ; DIMM_READ
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#define DIMM7_READ DIMM_BASE(7) ; DIMM_READ
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#define DIMMS_READ_EBX_OFFSET \
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DIMM0_READ ; \
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DIMM1_READ ; \
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DIMM2_READ ; \
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DIMM3_READ ; \
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DIMM4_READ ; \
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DIMM5_READ ; \
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DIMM6_READ ; \
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DIMM7_READ
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#define DIMMS_READ(offset) \
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movl $offset, %ebx ; \
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DIMMS_READ_EBX_OFFSET
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#define RAM_COMMAND_NONE 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x4
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#define SET_RAM_COMMAND(command) \
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movl $0x76, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x1F, %eax ; \
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orl $((command) << 5), %eax ; \
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movl %eax, %edx ; \
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movl $0x76, %eax ; \
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PCI_WRITE_CONFIG_BYTE
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#define COMPUTE_CAS_MODE \
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movl $0x76, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x4, %eax ; \
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xorl $0x4, %eax ; \
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shll $2, %eax ; \
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orl $0x2a, %eax ; \
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#define SET_RAM_MODE_REGISTER \
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SET_RAM_COMMAND(RAM_COMMAND_MRS) ; \
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COMPUTE_CAS_MODE ; \
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shll $3, %eax ; \
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movl %eax, %ebx ; \
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DIMMS_READ_EBX_OFFSET
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#define ASSERT_RAM_COMMAND() DIMMS_READ(RAM_READ)
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#define ASSERT_MRS_RAM_COMMAND(mode) DIMMS_READ(mode)
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#define ENABLE_REFRESH() CALL_LABEL(spd_enable_refresh)
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/* Default values for config registers */
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#define SET_NBXCFG \
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CS_WRITE_LONG(0x50, 0xff00a00c)
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#define SET_DRAMC \
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CS_WRITE_BYTE(0x57, 0x8) \
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/* PAM - Programmable Attribute Map Registers */
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/* Ideally we want to enable all of these as DRAM and teach
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* linux it is o.k. to use them...
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*/
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#define SET_PAM \
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CS_WRITE_BYTE(0x59, 0x00) ; \
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CS_WRITE_BYTE(0x5a, 0x00) ; \
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CS_WRITE_BYTE(0x5b, 0x00) ; \
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CS_WRITE_BYTE(0x5c, 0x00) ; \
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CS_WRITE_BYTE(0x5d, 0x00) ; \
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CS_WRITE_BYTE(0x5e, 0x00) ; \
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CS_WRITE_BYTE(0x5f, 0x00)
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#define SET_DRB \
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/* DRB - DRAM Row Boundary Registers */ \
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CS_WRITE_BYTE(0x60, DRB) ; \
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CS_WRITE_BYTE(0x61, DRB) ; \
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CS_WRITE_BYTE(0x62, DRB) ; \
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CS_WRITE_BYTE(0x63, DRB) ; \
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CS_WRITE_BYTE(0x64, DRB) ; \
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CS_WRITE_BYTE(0x65, DRB) ; \
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CS_WRITE_BYTE(0x66, DRB) ; \
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CS_WRITE_BYTE(0x67, DRB)
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#define SET_FDHC \
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CS_WRITE_BYTE(0x68, 0x00)
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#define SET_RPS \
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CS_WRITE_WORD(0x74, 0x0000)
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#define SET_SDRAMC \
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CS_WRITE_BYTE(0x76, 0x00)
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#define SET_PGPOL \
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CS_WRITE_WORD(0x78, 0xff00)
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/* PMCR - Power Management Control Register
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Enable normal refresh operation and
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the gated clock */
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#define SET_PMCR \
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CS_WRITE_BYTE(0x7a, 0x14)
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ram_set_registers:
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SET_NBXCFG
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SET_DRAMC
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SET_PAM
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SET_DRB
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SET_FDHC
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SET_RPS
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SET_SDRAMC
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SET_PGPOL
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SET_PMCR
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RET_LABEL(ram_set_registers)
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#define DEVFN(device, function) (((device) << 3) + (function))
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#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
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#define PM_FUNCTION CONFIG_ADDR(0, PIIX4_DEVFN+3, 0)
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#define SMBUS_IO_BASE 0x1000
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#define SMBHSTSTAT 0
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#define SMBHSTCTL 2
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#define SMBHSTCMD 3
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#define SMBHSTADD 4
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#define SMBHSTDAT0 5
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#define SMBHSTDAT1 6
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#define SMBBLKDAT 7
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enable_smbus:
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CS_WRITE_LONG(PM_FUNCTION + 0x90, SMBUS_IO_BASE | 1) /* iobase addr */
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CS_WRITE_BYTE(PM_FUNCTION + 0xd2, (0x4 << 1) | 1) /* smbus enable */
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CS_WRITE_WORD(PM_FUNCTION + 0x4, 1) /* iospace enable */
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RET_LABEL(enable_smbus)
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/*
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* Routine: setup_smbus
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* Arguments: none
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* Results: none
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* Trashed: eax, edx
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* Effects: The smbus is enabled
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*/
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setup_smbus:
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mov $0x1e, %al
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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outb %al, %dx
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RET_LABEL(setup_smbus)
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#define SMBUS_MEM_DEVICE_0 (0xa << 3)
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#define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1)
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#define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2)
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#define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3)
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smbus_wait_until_ready:
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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1: inb %dx, %al
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testb $1, %al
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jnz 1b
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RET_LABEL(smbus_wait_until_ready)
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smbus_wait_until_done:
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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1: inb %dx, %al
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testb $1, %al
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jnz 1b
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testb $0xfe, %al
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jz 1b /* wait until interrupt status is set */
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RET_LABEL(smbus_wait_until_done)
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smbus_read_byte:
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/* poll until the smbus is ready for commands */
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CALL_LABEL(smbus_wait_until_ready)
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/* clear any lingering errors, so that the transaction will run */
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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mov $0x1e, %al
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outb %al, %dx
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/* set the device I'm talking to */
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movl $(SMBUS_IO_BASE + SMBHSTADD), %edx
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movb %bl /* device */, %al
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shlb $1, %al
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orb $1, %al
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outb %al, %dx
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/* set the command address... */
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movl $(SMBUS_IO_BASE + SMBHSTCMD), %edx
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movb %bh /* address */, %al
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outb %al, %dx
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/* clear the data byte */
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movl $(SMBUS_IO_BASE + SMBHSTDAT0), %edx
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xorl %eax, %eax
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outb %al, %dx
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/* start a byte read, with interrupts disabled */
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movl $(SMBUS_IO_BASE + SMBHSTCTL), %edx
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movl $((0x2 << 2) | (1 << 6)), %eax
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outb %al, %dx
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/* poll for transaction completion */
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CALL_LABEL(smbus_wait_until_done)
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/* read the results and see if we succeded */
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1: movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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inb %dx, %al
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testb $0x04, %al
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jnz 1f
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movl $(SMBUS_IO_BASE + SMBHSTDAT0), %edx
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inb %dx, %al
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1:
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RETSP
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configure_rps_pgpol_drb:
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/* %bl is the row index */
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xorl %ebx, %ebx
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/* %si is the aggregation of bits for RPS */
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xorl %esi, %esi
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/* %di has bits to be set in PGPOL */
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xorl %edi, %edi
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/* %cx holds the cumulative memory size of DIMMs */
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xorl %ecx, %ecx
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next_row:
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movzx %bl, %dx
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shl $16, %ebx
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shr $1, %dx
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mov $((5 << 8) | SMBUS_MEM_DEVICE_0), %bx
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or %dx, %bx
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CALLSP(smbus_read_byte)
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jnz shift_before_moving_on
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shr $16, %ebx
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testb $2, %al
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jnz two_rows
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testb $1, %bl
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/* this used to be jnz but seems it should be jz */
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jz ready_for_next_row
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two_rows:
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movzx %bl, %dx
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shl $16, %ebx
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shr $1, %dx
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mov $((4 << 8) | SMBUS_MEM_DEVICE_0), %bx
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or %dx, %bx
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CALLSP(smbus_read_byte)
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shr $16, %ebx
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subb $8, %al
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shrd $2, %ax, %si
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movzx %bl, %dx
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shl $16, %ebx
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shr $1, %dx
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mov $((17 << 8) | SMBUS_MEM_DEVICE_0), %bx
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or %dx, %bx
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CALLSP(smbus_read_byte)
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shr $16, %ebx
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cmpb $4, %al
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sete %al
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shrd $1, %ax, %di
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movzx %bl, %dx
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shl $16, %ebx
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shr $1, %dx
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mov $((31 << 8) | SMBUS_MEM_DEVICE_0), %bx
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or %dx, %bx
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CALLSP(smbus_read_byte)
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shr $16, %ebx
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shr $1, %al
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xorb %ah, %ah
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add %ax, %cx
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movzx %cx, %edx
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movzx %bl, %eax
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addl $0x60, %eax
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PCI_WRITE_CONFIG_BYTE
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jmp 1f
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shift_before_moving_on:
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shr $16, %ebx
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ready_for_next_row:
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shr $2, %si
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shr $1, %di
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movzx %cx, %edx
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movzx %bl, %eax
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addl $0x60, %eax
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PCI_WRITE_CONFIG_BYTE
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1:
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inc %bl
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cmp MAX_ROWS, %bl
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jb next_row
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/* Now to finally write the RPS and PGPOL registers */
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movzx %si, %ecx
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movl $0x74, %eax
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PCI_WRITE_CONFIG_WORD
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mov %di, %cx
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movzx %ch, %edx
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movl $0x79, %eax
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PCI_WRITE_CONFIG_BYTE
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RET_LABEL(configure_rps_pgpol_drb)
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configure_sdramc:
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movl $((18 << 8) | SMBUS_MEM_DEVICE_0), %ebx
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0: CALLSP(smbus_read_byte)
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jnz 1f
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testb $2, %al
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jz 2f /* Default settings are OK if only CAS=3 is supported */
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movl $0x06, %edx
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movl $0x76, %eax
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PCI_WRITE_CONFIG_BYTE
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jmp 2f
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1: addl $1, %ebx /* increment the device */
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cmpb $SMBUS_MEM_DEVICE_3, %bl
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jbe 0b
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2:
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RET_LABEL(configure_sdramc)
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spd_set_dramc:
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movl $((21 << 8) | SMBUS_MEM_DEVICE_0), %ebx
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1: CALLSP(smbus_read_byte)
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jnz 2f
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andl $0x12, %eax
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jmp spd_set_dramc_out
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2: addl $1, %ebx /* increment the device */
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cmpb $SMBUS_MEM_DEVICE_3, %bl
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jbe 1b
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jmp no_memory
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spd_set_dramc_out:
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testb $0x2, %al
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movl $8, %eax
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jz 1f
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movl $0x10, %eax
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1: movl %eax, %edx
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movl $0x57, %eax
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PCI_WRITE_CONFIG_BYTE
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RET_LABEL(spd_set_dramc)
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/*
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* Routine: spd_enable_refresh
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* Arguments: None
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*
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* Trashed: %eax, %ebx, %ecx, %edx, %esp, %eflags
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* Effects: Uses serial presence detect to set the
|
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* refresh rate in the DRAMC register.
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* see spd_set_dramc for the other values.
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* FIXME: Check for illegal/unsupported ram configurations and abort
|
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*/
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||||
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refresh_rates:
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.byte 0x01 /* Normal 15.625 us -> 15.6 us */
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.byte 0x05 /* Reduced(.25X) 3.9 us -> 7.8 us */
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.byte 0x05 /* Reduced(.5X) 7.8 us -> 7.8 us */
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.byte 0x02 /* Extended(2x) 31.3 us -> 31.2 us */
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.byte 0x03 /* Extended(4x) 62.5 us -> 62.4 us */
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.byte 0x04 /* Extended(8x) 125 us -> 124.8 us */
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|
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spd_enable_refresh:
|
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/* Find the first dimm and assume the rest are the same */
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/* Load the smbus device and port int %ebx */
|
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movl $((12 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
||||
1: CALLSP(smbus_read_byte)
|
||||
jnz 2f
|
||||
andl $0x7f, %eax
|
||||
jmp spd_enable_refresh_out
|
||||
|
||||
2: addl $1, %ebx /* increment the device */
|
||||
cmpb $SMBUS_MEM_DEVICE_3, %bl
|
||||
jbe 1b
|
||||
/* We couldn't find anything we must have no memory */
|
||||
jmp no_memory
|
||||
|
||||
spd_enable_refresh_out:
|
||||
cmpb $0x06, %al
|
||||
ja 1f
|
||||
addl $refresh_rates, %eax
|
||||
movb (%eax), %cl
|
||||
jmp 2f
|
||||
1: movb $0x05, %cl
|
||||
2: movl $0x57, %eax
|
||||
PCI_READ_CONFIG_BYTE
|
||||
andb $0xf8, %al
|
||||
orb %cl, %al
|
||||
movb %al, %dl
|
||||
movl $0x57, %eax
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
RET_LABEL(spd_enable_refresh)
|
||||
|
||||
spd_set_nbxcfg:
|
||||
/* say all dimms have no ECC support */
|
||||
movl $0xFF, %esi
|
||||
/* Index into %esi of bit to set */
|
||||
movl $0 , %ecx
|
||||
/* Load the smbus device into %ebx */
|
||||
movl $SMBUS_MEM_DEVICE_0, %ebx
|
||||
|
||||
1: movb $11, %bh
|
||||
CALLSP(smbus_read_byte) /* module error correction type */
|
||||
jnz 2f
|
||||
cmp $0x2, %eax /* 0 == None, 1 == Parity, 2 == ECC */
|
||||
jne 2f
|
||||
movl $0x1, %eax
|
||||
shll %cl, %eax
|
||||
xorl %eax, %esi
|
||||
|
||||
/* side two */
|
||||
movb $5, %bh
|
||||
CALLSP(smbus_read_byte) /* number of physical banks */
|
||||
cmp $1, %al
|
||||
jbe 2f
|
||||
/* The only is the symmtrical case */
|
||||
movl $0x2, %eax
|
||||
shll %cl, %eax
|
||||
xorl %eax, %esi
|
||||
|
||||
2: addl $1, %ebx /* increment the device */
|
||||
addl $2, %ecx /* increment the shift count */
|
||||
cmpb $SMBUS_MEM_DEVICE_3, %bl
|
||||
jbe 1b
|
||||
|
||||
movl %esi, %edx
|
||||
movl $0x53, %eax
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
|
||||
movl $((126 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
||||
CALLSP(smbus_read_byte)
|
||||
|
||||
RET_LABEL(spd_set_nbxcfg)
|
||||
|
||||
ram_set_spd_registers:
|
||||
CALL_LABEL(enable_smbus)
|
||||
CALL_LABEL(setup_smbus)
|
||||
CALL_LABEL(configure_sdramc)
|
||||
CALL_LABEL(configure_rps_pgpol_drb)
|
||||
CALL_LABEL(spd_set_dramc)
|
||||
CALL_LABEL(spd_set_nbxcfg)
|
||||
|
||||
RET_LABEL(ram_set_spd_registers)
|
||||
|
||||
|
||||
/* things that are not used */
|
||||
#define FIRST_NORMAL_REFERENCE()
|
||||
#define SPECIAL_FINISHUP()
|
||||
|
||||
intel_430_out:
|
||||
|
||||
Loading…
Add table
Reference in a new issue