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mainboard/sunw/ultra40/romstage.c: Use tabs for indents

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Change-Id: I9b7be74625dfcb6317a1cdb61d0dc77d7f359462
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16776
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2016-09-27 21:28:57 +02:00 • committed by Martin Roth
parent 8f372d031b
commit 6da74da345
1 changed files with 48 additions and 48 deletions
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96
src/mainboard/sunw/ultra40/romstage.c
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@ -30,12 +30,12 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { }
#ifdef ENABLE_ONBOARD_SCSI #ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void) static void sio_gpio_setup(void)
{ {
unsigned value; unsigned value;
/*Enable onboard scsi*/ /*Enable onboard scsi*/
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1))); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1)));
} }
#endif #endif
@ -55,12 +55,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
//set GPIO to input mode //set GPIO to input mode
#define CK804_MB_SETUP \ #define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/early_setup_car.c" #include "southbridge/nvidia/ck804/early_setup_car.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
@ -68,25 +68,25 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20; byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
dword |= (1 << 29)|(1 << 0); dword |= (1 << 29)|(1 << 0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value &= 0xbf; value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
} }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@ -100,49 +100,49 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
DIMM5, DIMM7, 0, 0, DIMM5, DIMM7, 0, 0,
}; };
int needs_reset; int needs_reset;
unsigned bsp_apicid = 0, nodes; unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8]; struct mem_controller ctrl[8];
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
} }
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx); bsp_apicid = init_cpus(cpu_init_detectedx);
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
setup_ultra40_resource_map(); setup_ultra40_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS #if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
start_other_cores(); start_other_cores();
wait_all_other_cores_started(bsp_apicid); wait_all_other_cores_started(bsp_apicid);
#endif #endif
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n"); printk(BIOS_INFO, "ht reset -\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
nodes = get_nodes(); nodes = get_nodes();
//It's the time to set ctrl now; //It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr); fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus(); enable_smbus();