mirror of
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more ppc
This commit is contained in:
Greg Watson
parent
2041c328cd
commit
690d5777c7
3 changed files with 630 additions and 0 deletions
182
src/arch/ppc/include/arch/io.h
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182
src/arch/ppc/include/arch/io.h
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@ -0,0 +1,182 @@
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/*
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* BK Id: SCCS/s.io.h 1.14 10/16/01 15:58:42 trini
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*/
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#ifndef _PPC_IO_H
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#define _PPC_IO_H
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#include <types.h>
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#define SIO_CONFIG_RA 0x398
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#define SIO_CONFIG_RD 0x399
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#define SLOW_DOWN_IO
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#define PMAC_ISA_MEM_BASE 0
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#define PMAC_PCI_DRAM_OFFSET 0
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#define CHRP_ISA_IO_BASE 0xf8000000
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#define CHRP_ISA_MEM_BASE 0xf7000000
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#define CHRP_PCI_DRAM_OFFSET 0
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#define PREP_ISA_IO_BASE 0x80000000
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#define PREP_ISA_MEM_BASE 0xc0000000
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#define PREP_PCI_DRAM_OFFSET 0x80000000
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#define _IO_BASE 0xfe000000
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#define readb(addr) in_8((volatile u8 *)(addr))
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#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
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#define readw(addr) in_le16((volatile u16 *)(addr))
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#define readl(addr) in_le32((volatile u32 *)(addr))
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#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
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#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
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#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
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#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
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#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
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#define __raw_writeb(v, addr) (*(volatile unsigned char *)(addr) = (v))
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#define __raw_writew(v, addr) (*(volatile unsigned short *)(addr) = (v))
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#define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v))
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/*
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* The insw/outsw/insl/outsl macros don't do byte-swapping.
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* They are only used in practice for transferring buffers which
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* are arrays of bytes, and byte-swapping is not appropriate in
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* that case. - paulus
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*/
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#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define inb(port) in_8((u8 *)((port)+_IO_BASE))
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#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
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#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
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#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
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#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
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#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
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#define inb_p(port) inb((port))
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#define outb_p(val, port) outb((val), (port))
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#define inw_p(port) inw((port))
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#define outw_p(val, port) outw((val), (port))
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#define inl_p(port) inl((port))
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#define outl_p(val, port) outl((val), (port))
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extern void _insb(volatile u8 *port, void *buf, int ns);
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extern void _outsb(volatile u8 *port, const void *buf, int ns);
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extern void _insw(volatile u16 *port, void *buf, int ns);
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extern void _outsw(volatile u16 *port, const void *buf, int ns);
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extern void _insl(volatile u32 *port, void *buf, int nl);
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extern void _outsl(volatile u32 *port, const void *buf, int nl);
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extern void _insw_ns(volatile u16 *port, void *buf, int ns);
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extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
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extern void _insl_ns(volatile u32 *port, void *buf, int nl);
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extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
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/*
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* The *_ns versions below don't do byte-swapping.
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* Neither do the standard versions now, these are just here
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* for older code.
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*/
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#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define IO_SPACE_LIMIT ~0
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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/*
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* Enforce In-order Execution of I/O:
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* Acts as a barrier to ensure all previous I/O accesses have
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* completed before any further ones are issued.
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*/
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extern inline void eieio(void)
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{
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__asm__ __volatile__ ("eieio" : : : "memory");
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}
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/* Enforce in-order execution of data I/O.
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* No distinction between read/write on PPC; use eieio for all three.
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*/
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#define iobarrier_rw() eieio()
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#define iobarrier_r() eieio()
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#define iobarrier_w() eieio()
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/*
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* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
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*/
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extern inline int in_8(volatile unsigned char *addr)
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{
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int ret;
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__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_8(volatile unsigned char *addr, int val)
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{
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__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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extern inline int in_le16(volatile unsigned short *addr)
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{
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int ret;
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__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline int in_be16(volatile unsigned short *addr)
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{
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int ret;
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__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le16(volatile unsigned short *addr, int val)
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{
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__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be16(volatile unsigned short *addr, int val)
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{
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__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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extern inline unsigned in_le32(volatile unsigned *addr)
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{
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unsigned ret;
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__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline unsigned in_be32(volatile unsigned *addr)
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{
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unsigned ret;
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__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le32(volatile unsigned *addr, int val)
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{
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__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be32(volatile unsigned *addr, int val)
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{
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__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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#endif
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269
src/southbridge/winbond/w83c553/w83c553f.c
Normal file
269
src/southbridge/winbond/w83c553/w83c553f.c
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@ -0,0 +1,269 @@
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/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Initialisation of the PCI-to-ISA bridge and disabling the BIOS
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* write protection (for flash) in function 0 of the chip.
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* Enabling function 1 (IDE controller of the chip.
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*/
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#include <types.h>
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#include <arch/io.h>
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#include <pci.h>
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#include <printk.h>
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#include "w83c553f.h"
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#ifndef CONFIG_ISA_MEM
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#define CONFIG_ISA_MEM 0xFD000000
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#endif
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#ifndef CONFIG_ISA_IO
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#define CONFIG_ISA_IO 0xFE000000
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#endif
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#ifndef CONFIG_IDE_MAXBUS
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#define CONFIG_IDE_MAXBUS 2
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#endif
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#ifndef CONFIG_IDE_MAXDEVICE
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#define CONFIG_IDE_MAXDEVICE (CONFIG_IDE_MAXBUS*2)
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#endif
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u32 ide_bus_offset[CONFIG_IDE_MAXBUS];
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void initialise_pic(void);
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void initialise_dma(void);
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extern struct pci_ops pci_direct_ppc;
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void southbridge_early_init(void)
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{
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struct pci_dev *devbusfn;
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unsigned char reg8;
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unsigned short reg16;
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unsigned int reg32;
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/*
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* Set ISA memory space
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*/
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pci_direct_ppc.read_byte(0, 0x58, WINBOND_IPADCR, ®8);
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/* 16 MB ISA memory space */
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reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
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reg8 &= ~IPADCR_MBE512;
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pci_direct_ppc.read_byte(0, 0x58, WINBOND_IPADCR, reg8);
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}
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void southbridge_init(void)
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{
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struct pci_dev *devbusfn;
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unsigned char reg8;
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unsigned short reg16;
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unsigned int reg32;
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devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
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if (devbusfn == 0)
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{
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printk_info("Error: Cannot find W83C553F controller on any PCI bus\n");
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return;
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}
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printk_info("Found W83C553F controller\n");
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/* always enabled */
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#if 0
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
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#endif
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/*
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* Set ISA memory space
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*/
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pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8);
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/* 16 MB ISA memory space */
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reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
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reg8 &= ~IPADCR_MBE512;
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pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
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/*
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* Chip select: switch off BIOS write protection
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*/
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pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8);
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reg8 |= CSCR_UBIOSCSE;
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reg8 &= ~CSCR_BIOSWP;
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pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
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/*
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* Interrupt routing:
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* - IDE -> INTC/INTD
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* - INTA -> IRQ 5
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* - INTB -> IRQ 6
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* - INTC -> IRQ 7
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* - INTD -> IRQ 8
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*/
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pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x0);
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pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0x5678);
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/*
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* Read IDE bus offsets from function 1 device.
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* We must unmask the LSB indicating that it is an IO address.
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*/
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devbusfn = pci_find_device(W83C553F_VID, W83C553F_IDE, 0);
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if (devbusfn == 0)
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{
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printk_info("Error: Cannot find W83C553F function 1 device\n");
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return;
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}
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/*
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* Switch off legacy IRQ for IDE and IDE port 1.
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*/
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pci_write_config_byte(devbusfn, 0x09, 0x8F);
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/*
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* Set LEGIRQ (IDE->IRQD/E)
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* Disable secondary port ~P1EN (?)
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* Secondary port Mode 0 ~P1F16
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*/
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pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32);
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reg32 |= IDECSR_LEGIRQ;
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reg32 &= ~(IDECSR_P1EN | IDECSR_P1F16);
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pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
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ide_bus_offset[0] &= ~1;
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#if CONFIG_IDE_MAXBUS > 1
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
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ide_bus_offset[1] &= ~1;
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#endif
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/*
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* Enable function 1, IDE -> busmastering and IO space access
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*/
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
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/*
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* Initialise ISA interrupt controller
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*/
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initialise_pic();
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/*
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* Initialise DMA controller
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*/
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initialise_dma();
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printk_info("W83C553F configuration complete\n");
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}
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void initialise_pic(void)
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{
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outb(W83C553F_PIC1_ICW1, 0x11);
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outb(W83C553F_PIC1_ICW2, 0x08);
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outb(W83C553F_PIC1_ICW3, 0x04);
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outb(W83C553F_PIC1_ICW4, 0x01);
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outb(W83C553F_PIC1_OCW1, 0xfb);
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outb(W83C553F_PIC1_ELC, 0x20);
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outb(W83C553F_PIC2_ICW1, 0x11);
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outb(W83C553F_PIC2_ICW2, 0x08);
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outb(W83C553F_PIC2_ICW3, 0x02);
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outb(W83C553F_PIC2_ICW4, 0x01);
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outb(W83C553F_PIC2_OCW1, 0xff);
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outb(W83C553F_PIC2_ELC, 0xce);
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outb(W83C553F_TMR1_CMOD, 0x74);
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outb(W83C553F_PIC2_OCW1, 0x20);
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outb(W83C553F_PIC1_OCW1, 0x20);
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outb(W83C553F_PIC2_OCW1, 0x2b);
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outb(W83C553F_PIC1_OCW1, 0x2b);
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}
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void initialise_dma(void)
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{
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unsigned int channel;
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unsigned int rvalue1, rvalue2;
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/* perform a H/W reset of the devices */
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outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
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outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
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/* initialise all channels to a sane state */
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for (channel = 0; channel < 4; channel++) {
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/*
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* dependent upon the channel, setup the specifics:
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*
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* demand
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* address-increment
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* autoinitialize-disable
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* verify-transfer
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*/
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switch (channel) {
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case 0:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
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break;
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case 1:
|
||||
rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
|
||||
rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
|
||||
break;
|
||||
case 2:
|
||||
rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
|
||||
rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
|
||||
break;
|
||||
case 3:
|
||||
rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
|
||||
rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
|
||||
break;
|
||||
default:
|
||||
rvalue1 = 0x00;
|
||||
rvalue2 = 0x00;
|
||||
break;
|
||||
}
|
||||
|
||||
/* write to write mode registers */
|
||||
|
||||
outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
|
||||
outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
|
||||
}
|
||||
|
||||
/* enable all channels */
|
||||
|
||||
outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
|
||||
outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
|
||||
/*
|
||||
* initialize the global DMA configuration
|
||||
*
|
||||
* DACK# active low
|
||||
* DREQ active high
|
||||
* fixed priority
|
||||
* channel group enable
|
||||
*/
|
||||
|
||||
outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
|
||||
outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
|
||||
}
|
||||
179
src/southbridge/winbond/w83c553/w83c553f.h
Normal file
179
src/southbridge/winbond/w83c553/w83c553f.h
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* winbond access routines and defines*/
|
||||
|
||||
/* from the winbond data sheet -
|
||||
The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
|
||||
Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
|
||||
*/
|
||||
|
||||
/*ISA bridge configuration space*/
|
||||
|
||||
#define W83C553F_VID 0x10AD
|
||||
#define W83C553F_DID 0x0565
|
||||
#define W83C553F_IDE 0x0105
|
||||
|
||||
#define WINBOND_PCICONTR 0x40 /*pci control reg*/
|
||||
#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
|
||||
#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
|
||||
#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
|
||||
#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
|
||||
#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
|
||||
#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
|
||||
#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
|
||||
#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
|
||||
#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
|
||||
#define WINBOND_CDR 0x4c /*Clock Divisor Register*/
|
||||
#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
|
||||
#define WINBOND_ATSCR 0x4e /*AT System Control register*/
|
||||
#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
|
||||
#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
|
||||
#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
|
||||
#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
|
||||
#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
|
||||
|
||||
#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
|
||||
|
||||
#define IPADCR_MBE512 0x1
|
||||
#define IPADCR_MBE640 0x2
|
||||
#define IPADCR_IPATOM4 0x10
|
||||
#define IPADCR_IPATOM5 0x20
|
||||
#define IPADCR_IPATOM6 0x40
|
||||
#define IPADCR_IPATOM7 0x80
|
||||
|
||||
#define CSCR_UBIOSCSE 0x10
|
||||
#define CSCR_BIOSWP 0x20
|
||||
|
||||
#define IDECSR_P0EN 0x01
|
||||
#define IDECSR_P0F16 0x02
|
||||
#define IDECSR_P1EN 0x10
|
||||
#define IDECSR_P1F16 0x20
|
||||
#define IDECSR_LEGIRQ 0x800
|
||||
|
||||
/*
|
||||
* Interrupt controller
|
||||
*/
|
||||
#define W83C553F_PIC1_ICW1 CONFIG_ISA_IO + 0x20
|
||||
#define W83C553F_PIC1_ICW2 CONFIG_ISA_IO + 0x21
|
||||
#define W83C553F_PIC1_ICW3 CONFIG_ISA_IO + 0x21
|
||||
#define W83C553F_PIC1_ICW4 CONFIG_ISA_IO + 0x21
|
||||
#define W83C553F_PIC1_OCW1 CONFIG_ISA_IO + 0x21
|
||||
#define W83C553F_PIC1_OCW2 CONFIG_ISA_IO + 0x20
|
||||
#define W83C553F_PIC1_OCW3 CONFIG_ISA_IO + 0x20
|
||||
#define W83C553F_PIC1_ELC CONFIG_ISA_IO + 0x4D0
|
||||
#define W83C553F_PIC2_ICW1 CONFIG_ISA_IO + 0xA0
|
||||
#define W83C553F_PIC2_ICW2 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_ICW3 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_ICW4 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_OCW1 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_OCW2 CONFIG_ISA_IO + 0xA0
|
||||
#define W83C553F_PIC2_OCW3 CONFIG_ISA_IO + 0xA0
|
||||
#define W83C553F_PIC2_ELC CONFIG_ISA_IO + 0x4D1
|
||||
|
||||
#define W83C553F_TMR1_CMOD CONFIG_ISA_IO + 0x43
|
||||
|
||||
/*
|
||||
* DMA controller
|
||||
*/
|
||||
#define W83C553F_DMA1 CONFIG_ISA_IO + 0x000 /* channel 0 - 3 */
|
||||
#define W83C553F_DMA2 CONFIG_ISA_IO + 0x0C0 /* channel 4 - 7 */
|
||||
|
||||
/* command/status register bit definitions */
|
||||
|
||||
#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
|
||||
#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
|
||||
#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
|
||||
#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
|
||||
|
||||
#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
|
||||
#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
|
||||
#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
|
||||
#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
|
||||
|
||||
#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
|
||||
#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
|
||||
#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
|
||||
#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
|
||||
|
||||
/* mode register bit definitions */
|
||||
|
||||
#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
|
||||
#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
|
||||
#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
|
||||
#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
|
||||
#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
|
||||
#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
|
||||
#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
|
||||
#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
|
||||
#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
|
||||
#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
|
||||
#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||
#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||
#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||
#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||
|
||||
/* request register bit definitions */
|
||||
|
||||
#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
|
||||
#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||
#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||
#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||
#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||
|
||||
/* write single mask bit register bit definitions */
|
||||
|
||||
#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
|
||||
#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||
#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||
#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||
#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||
|
||||
/* read/write all mask bits register bit definitions */
|
||||
|
||||
#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
|
||||
#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
|
||||
#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
|
||||
#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
|
||||
|
||||
/* typedefs */
|
||||
|
||||
#define W83C553F_DMA1_CS 0x8
|
||||
#define W83C553F_DMA1_WR 0x9
|
||||
#define W83C553F_DMA1_WSMB 0xA
|
||||
#define W83C553F_DMA1_WM 0xB
|
||||
#define W83C553F_DMA1_CBP 0xC
|
||||
#define W83C553F_DMA1_MC 0xD
|
||||
#define W83C553F_DMA1_CM 0xE
|
||||
#define W83C553F_DMA1_RWAMB 0xF
|
||||
|
||||
#define W83C553F_DMA2_CS 0xD0
|
||||
#define W83C553F_DMA2_WR 0xD2
|
||||
#define W83C553F_DMA2_WSMB 0xD4
|
||||
#define W83C553F_DMA2_WM 0xD6
|
||||
#define W83C553F_DMA2_CBP 0xD8
|
||||
#define W83C553F_DMA2_MC 0xDA
|
||||
#define W83C553F_DMA2_CM 0xDC
|
||||
#define W83C553F_DMA2_RWAMB 0xDE
|
||||
|
||||
void initialise_w83c553f(void);
|
||||
Loading…
Add table
Reference in a new issue