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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
fix the !@#$#!@$ EPIA-M serial
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parent
5c25fa0ec0
commit
65648be911
1 changed files with 4 additions and 4 deletions
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@ -16,9 +16,9 @@
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movl $dword, %ecx ; \
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PCI_WRITE_CONFIG_DWORD
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#define DEVFN(device, function) (((device) << 3) + (function))
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#define DEVFN(device, function) (((device) << 3) + (function))
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#ifndef CONFIG_ADDR
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#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
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#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
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#endif
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/* generic SMB routines that work for many systems. The only one that might
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@ -45,7 +45,7 @@
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/* put the SMBUS at port 0xf00 + enable*/
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CS_WRITE_WORD(PM_DEVFN+ 0xd0, SMBUS_IO_BASE|1) /* iobase addr */
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CS_WRITE_BYTE(PM_DEVFN + 0xd2, (0x4 << 1) | 1) /* smbus enable */
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CS_WRITE_BYTE(PM_DEVFN + 0xd2, (0x4 << 1) | 1) /* smbus enable */
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CS_WRITE_WORD(PM_DEVFN + 0x4, 1) /* iospace enable */
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/* The VT1211 serial port needs 48 mhz clock, on power up it is getting
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@ -61,7 +61,7 @@
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MYOUTB( $0xff, $(SMBUS_IO_BASE+SMBHSTSTAT))
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MYOUTB( $0x7f, $(SMBUS_IO_BASE+SMBHSTDAT0))
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MYOUTB( $0x83, $(SMBUS_IO_BASE+SMBHSTCMD))
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MYOUTB( $(CLOCK_SLAVE_ADDRESS<<1), $(SMBUS_IO_BASE+SMBHSTADD))
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MYOUTB( $(CLOCK_SLAVE_ADDRESS<<1), $(SMBUS_IO_BASE+SMBHSTADD))
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MYOUTB( $(8 | I2C_TRANS_CMD), $(SMBUS_IO_BASE+SMBHSTCTL))
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movw $(SMBUS_IO_BASE+SMBHSTSTAT), %dx
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smbwait1:
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