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ipl.S: disable unstable SR13 SR14 programming

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irq_tables.c: updated IRQ routing
mainboard.c: don't disable flash write
This commit is contained in:
Li-Ta Lo 2002-08-01 07:48:53 +00:00
parent 131a050256
commit 64ce5d45ff
3 changed files with 3 additions and 5 deletions
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4
src/mainboard/bcm/e100/ipl.S
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@ -58,7 +58,7 @@ lpc_init_start: # inits LPC bridge for accessing
lpc_init_complete:
#if 0
SET_VGA_SR13:
movw $0x03c4,%dx #SR5
movb $0x05,%al
@ -373,7 +373,7 @@ Clock_Gen_Exit:
#endif
movw $0x5501, %ax # MDOE# enable, this bit
CALL_SP(write_pci_register) # should be set before sizing.

2
src/mainboard/bcm/e100/irq_tables.c
View file

@ -17,7 +17,7 @@ const struct irq_routing_table intel_irq_routing_table = {
/* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, 0x48, {{0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}},
0x01, 0x00},
{0x00, 0x58, {{0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}},
{0x00, 0x58, {{0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}},
0x00, 0x00},
{0x00, 0x68, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
0x00, 0x00},

2
src/mainboard/bcm/e100/mainboard.c
View file

@ -217,8 +217,6 @@ mainboard_fixup(void)
pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, (void *)NULL);
pci_read_config_word(pcidev, 0x74, &acpibase);
/* Flash can not be flashed, enable USB device in undocumented Bit 6 */
pci_write_config_byte(pcidev, 0x45, 0xA0);
led_on(10);