mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
major cleanup
This commit is contained in:
Andrew Ip
parent
5f2d733946
commit
64007a8e44
1 changed files with 3 additions and 321 deletions
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@ -35,19 +35,16 @@ void usb_on()
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/* enable USB1 */
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if(dev1) {
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pci_write_config_byte(dev1, 0x3c, 0x05);
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pci_write_config_byte(dev1, 0x04, 0x07);
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}
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/* enable USB2 */
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if(dev2) {
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pci_write_config_byte(dev2, 0x3c, 0x05);
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pci_write_config_byte(dev2, 0x04, 0x07);
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}
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/* enable USB3 */
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if(dev3) {
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pci_write_config_byte(dev3, 0x3c, 0x05);
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pci_write_config_byte(dev3, 0x04, 0x07);
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}
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@ -101,98 +98,6 @@ void nvram_on()
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{
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}
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/*
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* Enable the ethernet device and turn off stepping (because it is integrated
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* inside the southbridge)
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*/
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void ethernet_fixup()
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{
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struct pci_dev *dev, *edev;
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u8 byte;
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printk_info("Ethernet fixup\n");
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edev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3065, 0);
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if (edev != NULL) {
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printk_debug("Configuring VIA LAN\n");
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#if 0
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/* We don't need stepping - though the device supports it */
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pci_read_config_byte(edev, PCI_COMMAND, &byte);
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byte &= ~PCI_COMMAND_WAIT;
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pci_write_config_byte(edev, PCI_COMMAND, byte);
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/* turn on master and pio */
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pci_read_config_byte(edev, PCI_COMMAND, &byte);
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byte = byte | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
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pci_write_config_byte(edev, PCI_COMMAND, byte);
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#endif
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} else {
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printk_debug("VIA LAN not found\n");
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}
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}
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#if 1
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void southbridge_fixup()
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{
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unsigned char enables;
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struct pci_dev *dev0;
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struct pci_dev *dev1;
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struct pci_dev *devpwr;
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#if 0
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/* Base 8235 controller */
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dev0 = pci_find_device(PCI_VENDOR_ID_VIA, 0x3177, 0);
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/* IDE controller */
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dev1 = pci_find_device(PCI_VENDOR_ID_VIA, 0x0571, 0);
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/* Map 4MB of FLASH into the address space */
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pci_write_config_byte(dev0, 0x41, 0x7f);
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/* these follows award's values */
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pci_write_config_byte(dev0, 0x40, 0x45);
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pci_write_config_byte(dev0, 0x42, 0xf0);
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pci_write_config_byte(dev0, 0x4e, 0x0a);
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pci_write_config_byte(dev0, 0x4f, 0x08);
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pci_write_config_byte(dev0, 0x50, 0x81);
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pci_write_config_byte(dev0, 0x51, 0x1d);
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// pci_write_config_byte(dev0, 0x52, 0x09);
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pci_write_config_byte(dev0, 0x53, 0x00);
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pci_write_config_byte(dev0, 0x58, 0x20);
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pci_write_config_byte(dev0, 0x5b, 0x00);
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/* ide */
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/* these follows award's values */
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pci_write_config_byte(dev1, 0x40, 0x03);
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pci_write_config_byte(dev1, 0x41, 0xf2);
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pci_write_config_byte(dev1, 0x42, 0x09);
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pci_write_config_byte(dev1, 0x43, 0x05);
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pci_write_config_byte(dev1, 0x44, 0x18);
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pci_write_config_byte(dev1, 0x45, 0x1c);
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pci_write_config_byte(dev1, 0x4b, 0xa8);
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pci_write_config_byte(dev1, 0x4c, 0x3f);
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pci_write_config_byte(dev1, 0x4f, 0x20);
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pci_write_config_byte(dev1, 0x50, 0x17);
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pci_write_config_byte(dev1, 0x51, 0x17);
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pci_write_config_byte(dev1, 0x52, 0x17);
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pci_write_config_byte(dev1, 0x53, 0xe2);
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pci_write_config_byte(dev1, 0x54, 0x0c);
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pci_write_config_byte(dev1, 0x55, 0x03);
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/* Use compatability mode - per award bios */
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pci_write_config_dword(dev1, 0x10, 0x0);
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pci_write_config_dword(dev1, 0x14, 0x0);
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pci_write_config_dword(dev1, 0x18, 0x0);
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pci_write_config_dword(dev1, 0x1c, 0x0);
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ethernet_fixup();
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usb_on();
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#endif
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}
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#else
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void southbridge_fixup()
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{
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unsigned char enables;
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@ -206,11 +111,10 @@ void southbridge_fixup()
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dev1 = pci_find_device(PCI_VENDOR_ID_VIA, 0x0571, 0);
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/* enable the internal I/O decode */
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#if 0
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enables = pci_read_config_byte(dev0, 0x6C, &enables);
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enables |= 0x80;
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pci_write_config_byte(dev0, 0x6C, enables);
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#endif
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/* follow award */
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enables = pci_read_config_byte(dev0, 0x6C, &enables);
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enables = 0x00;
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@ -218,8 +122,6 @@ void southbridge_fixup()
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/* Map 4MB of FLASH into the address space */
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pci_write_config_byte(dev0, 0x41, 0x7f);
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/* let's try 0x0 to see what's happen */
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// pci_write_config_byte(dev0, 0x41, 0x00);
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/*
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* Set bit 6 of 0x40, because Award does it (IO recovery time)
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@ -235,26 +137,14 @@ void southbridge_fixup()
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enables |= 0xf0;
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pci_write_config_byte(dev0, 0x42, enables);
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/* Set bit 3 of 0x4a, to match award (dummy pci request) */
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// enables = pci_read_config_byte(dev0, 0x4a, &enables);
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// enables |= 0x08;
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// pci_write_config_byte(dev0, 0x4a, enables);
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/* Set 0x58 to 0x03 to match Award */
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pci_write_config_byte(dev0, 0x58, 0x03);
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/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
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enables = pci_read_config_byte(dev0, 0x4f, &enables);
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enables |= 0x08;
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pci_write_config_byte(dev0, 0x4f, enables);
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/* Set 0x58 to 0x03 to match Award */
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pci_write_config_byte(dev0, 0x58, 0x03);
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#if 0
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/* enable the ethernet/RTC */
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if(dev0) {
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pci_read_config_byte(dev0, 0x51, &enables);
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enables |= 0x18;
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pci_write_config_byte(dev0, 0x51, enables);
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}
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#endif
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#ifndef DISABLE_SOUTHBRIDGE_COM_PORTS
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/* enable com1 and com2. */
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enables = pci_read_config_byte(dev0, 0x6e, &enables);
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@ -262,10 +152,6 @@ void southbridge_fixup()
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* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 is enable
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* com port a as com1
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*/
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#if 0
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enables = 0x80 | 0x10 | 0x8 ;
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pci_write_config_byte(dev0, 0x6e, enables);
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#endif
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/* following award */
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enables = 0x00;
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pci_write_config_byte(dev0, 0x6e, enables);
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@ -278,136 +164,19 @@ void southbridge_fixup()
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*/
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#endif
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/*
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* enable IDE, since Linux won't do it.
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* First do some more things to devfn (17,0)
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* note: this should already be cleared, according to the book.
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*/
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pci_read_config_byte(dev0, 0x50, &enables);
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printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
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enables &= ~8; // need manifest constant here!
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printk_debug("set IDE reg. 50 to 0x%x\n", enables);
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pci_write_config_byte(dev0, 0x50, enables);
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/* moved it to setupide.inc */
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#if 0
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/* set default interrupt values (IDE) */
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pci_read_config_byte(dev0, 0x4c, &enables);
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printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
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/* clear out whatever was there. */
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enables &= ~0xf;
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enables = 44;
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printk_debug("setting reg. 4c to 0x%x\n", enables);
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pci_write_config_byte(dev0, 0x4c, enables);
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#endif
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#if 1
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/* enable serial irq */
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pci_write_config_byte(dev0, 0x52, 0x09);
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/* dma */
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pci_write_config_byte(dev0, 0x53, 0x00);
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/* diskable dynamic clock stop */
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pci_write_config_byte(dev0, 0x5b, 0x00);
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// pci_write_config_byte(dev0, 0x6c, 0x00);
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// pci_write_config_byte(dev0, 0x6e, 0x00);
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/*
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* set up the serial port interrupts.
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* com2 to 3, com1 to 4
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*/
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// pci_write_config_byte(dev0, 0x46, 0x04);
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// pci_write_config_byte(dev0, 0x47, 0x03);
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#endif
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#if 1
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/*
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* IDE setup
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*/
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#if !(ENABLE_IDE_NATIVE_MODE)
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/*
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* Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
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* interrupts. Using PCI ints confuses linux for some reason.
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*/
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pci_read_config_byte(dev1, 0x42, &enables);
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printk_debug("enables in reg 0x42 0x%x\n", enables);
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enables &= ~0xc0;
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pci_write_config_byte(dev1, 0x42, enables);
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pci_read_config_byte(dev1, 0x42, &enables);
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printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
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#endif
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pci_read_config_byte(dev1, 0x40, &enables);
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printk_debug("enables in reg 0x40 0x%x\n", enables);
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enables |= 3;
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pci_write_config_byte(dev1, 0x40, enables);
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pci_read_config_byte(dev1, 0x40, &enables);
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printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
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/* Enable prefetch buffers */
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pci_read_config_byte(dev1, 0x41, &enables);
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enables |= 0xf0;
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pci_write_config_byte(dev1, 0x41, enables);
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/* Lower thresholds (cause award does it) */
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pci_read_config_byte(dev1, 0x43, &enables);
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enables &= ~0x0f;
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enables |= 0x05;
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pci_write_config_byte(dev1, 0x43, enables);
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/* PIO read prefetch counter (cause award does it) */
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pci_write_config_byte(dev1, 0x44, 0x18);
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/* Use memory read multiple */
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pci_write_config_byte(dev1, 0x45, 0x1c);
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/* address decoding. */
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pci_read_config_byte(dev1, 0x9, &enables);
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printk_debug("enables in reg 0x9 0x%x\n", enables);
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/* by the book, set the low-order nibble to 0xa. */
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#if ENABLE_IDE_NATIVE_MODE
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enables &= ~0xf;
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/* cf/cg silicon needs an 'f' here. */
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enables |= 0xf;
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#else
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enables &= ~0x5;
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#endif
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pci_write_config_byte(dev1, 0x9, enables);
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pci_read_config_byte(dev1, 0x9, &enables);
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printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
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/* standard bios sets master bit. */
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pci_read_config_byte(dev1, 0x4, &enables);
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printk_debug("command in reg 0x4 0x%x\n", enables);
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enables |= 5;
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#if 1
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/* No need for stepping - kevinh@ispiri.com */
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enables &= ~0x80;
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#endif
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pci_write_config_byte(dev1, 0x4, enables);
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pci_read_config_byte(dev1, 0x4, &enables);
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printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
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#if (!ENABLE_IDE_NATIVE_MODE)
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/* Use compatability mode - per award bios */
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pci_write_config_dword(dev1, 0x10, 0x0);
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pci_write_config_dword(dev1, 0x14, 0x0);
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pci_write_config_dword(dev1, 0x18, 0x0);
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pci_write_config_dword(dev1, 0x1c, 0x0);
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/* Force interrupts to use compat mode - just like Award bios */
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/* !!! FIX moved it to ide_config.inc */
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#if 0
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pci_write_config_byte(dev1, 0x3d, 0x0);
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pci_write_config_byte(dev1, 0x3c, 0xff);
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#endif
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#endif
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#endif
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ethernet_fixup();
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usb_on();
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@ -416,90 +185,3 @@ void southbridge_fixup()
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rtc_init(0);
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#endif
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}
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#endif
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#if 0
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pci_write_config_byte(dev1, 0x40, 0x0b);
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pci_write_config_byte(dev1, 0x41, 0xf2);
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pci_write_config_byte(dev1, 0x42, 0x09);
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pci_write_config_byte(dev1, 0x43, 0x05);
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pci_write_config_byte(dev1, 0x44, 0x18);
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pci_write_config_byte(dev1, 0x45, 0x1c);
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pci_write_config_byte(dev1, 0x4b, 0xa8);
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pci_write_config_byte(dev1, 0x4c, 0x3f);
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pci_write_config_byte(dev1, 0x4f, 0x20);
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pci_write_config_byte(dev1, 0x50, 0x17);
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pci_write_config_byte(dev1, 0x51, 0x17);
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pci_write_config_byte(dev1, 0x52, 0x17);
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pci_write_config_byte(dev1, 0x53, 0xe2);
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pci_write_config_byte(dev1, 0x54, 0x0c);
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pci_write_config_byte(dev1, 0x55, 0x03);
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pci_write_config_byte(dev0, 0x6C, 0x00);
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pci_write_config_byte(dev0, 0x41, 0x7f);
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enables = pci_read_config_byte(dev0, 0x40, &enables);
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enables |= 0x45;
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pci_write_config_byte(dev0, 0x40, enables);
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enables = pci_read_config_byte(dev0, 0x42, &enables);
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enables |= 0xf0;
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pci_write_config_byte(dev0, 0x42, enables);
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enables = pci_read_config_byte(dev0, 0x4f, &enables);
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enables |= 0x08;
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pci_write_config_byte(dev0, 0x4f, enables);
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pci_write_config_byte(dev0, 0x58, 0x03);
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enables = pci_read_config_byte(dev0, 0x6e, &enables);
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enables = 0x00;
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pci_write_config_byte(dev0, 0x6e, enables);
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pci_read_config_byte(dev0, 0x50, &enables);
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enables &= ~8; // need manifest constant here!
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pci_write_config_byte(dev0, 0x50, enables);
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pci_write_config_byte(dev0, 0x52, 0x09);
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pci_write_config_byte(dev0, 0x53, 0x00);
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pci_write_config_byte(dev0, 0x5b, 0x00);
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pci_read_config_byte(dev1, 0x42, &enables);
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enables &= ~0xc0;
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pci_write_config_byte(dev1, 0x42, enables);
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pci_read_config_byte(dev1, 0x40, &enables);
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enables |= 3;
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pci_write_config_byte(dev1, 0x40, enables);
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pci_read_config_byte(dev1, 0x41, &enables);
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enables |= 0xf0;
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pci_write_config_byte(dev1, 0x41, enables);
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pci_read_config_byte(dev1, 0x43, &enables);
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enables &= ~0x0f;
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enables |= 0x05;
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pci_write_config_byte(dev1, 0x43, enables);
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pci_write_config_byte(dev1, 0x44, 0x18);
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pci_write_config_byte(dev1, 0x45, 0x1c);
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pci_read_config_byte(dev1, 0x9, &enables);
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enables &= ~0x5;
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pci_write_config_byte(dev1, 0x9, enables);
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pci_read_config_byte(dev1, 0x4, &enables);
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printk_debug("command in reg 0x4 0x%x\n", enables);
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enables |= 5;
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enables &= ~0x80;
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pci_write_config_byte(dev1, 0x4, enables);
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pci_write_config_dword(dev1, 0x10, 0x0);
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pci_write_config_dword(dev1, 0x14, 0x0);
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pci_write_config_dword(dev1, 0x18, 0x0);
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pci_write_config_dword(dev1, 0x1c, 0x0);
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#endif
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