apply a little more polish

Change-Id: If782f24db321d5fb4b6554f722742190f7238aee

src/mainboard/nintendo/switch/Makefile.inc

@@ -27,7 +27,7 @@ subdirs-y += bct
 bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
-bootblock-y += cbfs_switch.c
+bootblock-y += cbfs_usb.c
 
 verstage-y += reset.c
 
@@ -35,13 +35,13 @@ romstage-y += pmic.c
 romstage-y += reset.c
 romstage-y += romstage.c
 romstage-y += sdram_configs.c
-romstage-y += cbfs_switch.c
+romstage-y += cbfs_usb.c
 
 ramstage-y += mainboard.c
 ramstage-y += reset.c
 ramstage-y += pmic.c
 ramstage-y += sdram_configs.c
-ramstage-y += cbfs_switch.c
+ramstage-y += cbfs_usb.c
 
 bootblock-y += memlayout.ld
 romstage-y += memlayout.ld

src/mainboard/nintendo/switch/bootblock.c

@@ -113,7 +113,7 @@ void bootblock_mainboard_init(void)
 
 	soc_configure_funits(funits, ARRAY_SIZE(funits));
 
-	/* Reset PMIC so it works as expected on a warmboot */
+	/* PMIC requires a reset on a warmboot */
 	info->reset_func(info->reset_bit);
 	i2c_init(I2CPWR_BUS);
 	pmic_init(I2CPWR_BUS);

src/mainboard/nintendo/switch/cbfs.h

@@ -13,9 +13,9 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __MAINBOARD_NINTENDO_SWITCH_CBFS_SWITCH_H__
-#define __MAINBOARD_NINTENDO_SWITCH_CBFS_SWITCH_H__
+#ifndef __MAINBOARD_NINTENDO_SWITCH_CBFS_H__
+#define __MAINBOARD_NINTENDO_SWITCH_CBFS_H__
 
 void cbfs_switch_to_sdram(void);
 
-#endif /* __MAINBOARD_NINTENDO_SWITCH_CBFS_SWITCH_H__ */
+#endif /* __MAINBOARD_NINTENDO_SWITCH_CBFS_H__ */

src/mainboard/nintendo/switch/cbfs_usb.c

@@ -14,11 +14,22 @@
  */
 
 #include <boot_device.h>
+#include <soc/addressmap.h>
 #include <string.h>
 #include <symbols.h>
 
-#include "cbfs_switch.h"
+#include "cbfs.h"
 
+/* This allows a USB firmware upload:
+ * The BootROM is used to exchange data with the host. Since ramstage runs
+ * on CCPLEX we need to make sure to use the BootROM only on BPMP.
+ * romstage switches to a SDRAM backed CBFS for that reason, and ramstage then
+ * uses that exclusively.
+ */
+
+#define BOOTROM_RCM_TRANSPORT_ADDR	(TEGRA_SRAM_BASE + 0x3114)
+
+/* The used memory regions as defined in memlayout.ld */
 extern uint8_t _usb_bounce[];
 extern uint8_t _eusb_bounce[];
 #define _usb_bounce_size (_eusb_bounce - _usb_bounce)
@@ -27,9 +38,7 @@ extern uint8_t _rom_copy[];
 extern uint8_t _erom_copy[];
 #define _rom_copy_size (_erom_copy - _rom_copy)
 
-#define BOOTROM_RCM_TRANSPORT_ADDR	0x40003114
-
-/* The RCM struct of the BootROM */
+/* The RCM USB transport struct of the BootROM */
 static const struct {
 	char is_usb3;
 	char init_hw_done;
@@ -78,16 +87,17 @@ static ssize_t usb_readat(const struct region_device *rd, void *b,
 	size_t left = size;
 	size_t chunk;
 
+	/* A request consists of 8 bytes:
+	 * - offset, unsigned 32bit
+	 * - size, unsigned 32bit
+	 * Each as big endian on the wire.
+	 */
 	bounce_bewrite32(0, offset);
 	bounce_bewrite32(4, size);
 	rom_sendbuf(_usb_bounce, 8);
 
 	while (left > 0) {
-		chunk = left;
-		if (chunk > _usb_bounce_size)
-			chunk = _usb_bounce_size;
-
-		chunk = rom_recvbuf(_usb_bounce, chunk);
+		chunk = rom_recvbuf(_usb_bounce, min(left, _usb_bounce_size));
 		memcpy(b, _usb_bounce, chunk);
 
 		b += chunk;
@@ -109,9 +119,6 @@ static struct mmap_helper_region_device mdev_usb =
 static struct mem_region_device mdev_sdram =
 	MEM_REGION_DEV_RO_INIT(_rom_copy, CONFIG_ROM_SIZE);
 
-/* romstage start out with USB but switches to SDRAM.
- * ramstage uses SDRAM backed CBFS exclusively.
- */
 #if ENV_RAMSTAGE
 static bool rom_in_sdram = true;
 #else

src/mainboard/nintendo/switch/romstage.c

@@ -24,7 +24,7 @@
 #include <soc/padconfig.h>
 #include <soc/romstage.h>
 
-#include "cbfs_switch.h"
+#include "cbfs.h"
 #include "gpio.h"
 #include "pmic.h"
 

src/mainboard/nintendo/switch/sdram_configs.c

@@ -32,26 +32,21 @@ static const struct sdram_params sdram_configs[] = {
 #define FUSE_BASE		((void *)TEGRA_FUSE_BASE)
 #define  FUSE_RESERVED_ODM4	0x1d8
 
-static uint32_t switch_sdram_get_id(void)
+uint32_t ram_code(void)
 {
 	return (read32(FUSE_BASE + FUSE_RESERVED_ODM4) >> 3) & 7;
 }
 
 const struct sdram_params *get_sdram_config()
 {
-	uint32_t id = switch_sdram_get_id();
+	uint32_t rc = ram_code();
 
-	printk(BIOS_INFO, "Fuse SDRAM ID: %d\n", id);
+	printk(BIOS_INFO, "Fuse SDRAM code: %d\n", rc);
 
-	if (id >= ARRAY_SIZE(sdram_configs) ||
-		sdram_configs[id].MemoryType == NvBootMemoryType_Unused) {
-		die("Invalid SDRAM ID.");
+	if (rc >= ARRAY_SIZE(sdram_configs) ||
+		sdram_configs[rc].MemoryType == NvBootMemoryType_Unused) {
+		die("Invalid SDRAM code.");
 	}
 
-	return &sdram_configs[id];
-}
-
-uint32_t ram_code(void)
-{
-	return switch_sdram_get_id();
+	return &sdram_configs[rc];
 }