mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
FIXED! It only took 3 years ....
This commit is contained in:
Ronald G. Minnich
parent
4ddbdc1f98
commit
6280975dbf
2 changed files with 395 additions and 129 deletions
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@ -4,22 +4,164 @@
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#include <pci.h>
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#include <pciconf.h>
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/*
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* Automatic memory configuration by SONE Takeshi <ts1@tsn.or.jp>, 05/19/03
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*/
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static unsigned long find_size(unsigned long addr, unsigned long minimum)
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{
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unsigned long i;
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unsigned long maximum;
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volatile long *p;
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/* First, see if there is any RAM. */
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p = (long *) (addr + minimum);
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*p = 0x12345678;
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p = (long *) (addr + minimum + 8);
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*p = 0x87654321;
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p = (long *) (addr + minimum);
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if (*p != 0x12345678)
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return 0; /* No memory */
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maximum = (0xffUL << 23) - addr;
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/* Write to addresses with only one address bit on,
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* in increasing order, from address 8 (assuming 64-bit bus),
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* then read address zero to see if it gets wrap-around.
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* This way we can detect missing address bit due to incorrect
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* MA mapping, or the size of bank when MA mapping is correct. */
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for (i = 8; i < maximum; i <<= 1) {
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if (i < minimum)
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continue;
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p = (long *) (addr + i);
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*p = 0x89abcdef;
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p = (long *) addr;
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if (*p == 0x89abcdef)
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return i;
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}
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return maximum;
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}
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static void set_ma_mapping(struct pci_dev *pcidev, int bank, int type)
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{
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unsigned char reg, val;
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int shift;
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reg = 0x58 + bank/4;
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if (bank%4 >= 2)
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shift = 0;
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else
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shift = 4;
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pci_read_config_byte(pcidev, reg, &val);
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val &= ~(0xf << shift);
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val |= type << shift;
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pci_write_config_byte(pcidev, reg, val);
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}
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static int get_ma_mapping(struct pci_dev *pcidev, int bank)
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{
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unsigned char reg, val;
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int shift;
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reg = 0x58 + bank/4;
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if (bank%4 >= 2)
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shift = 0;
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else
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shift = 4;
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pci_read_config_byte(pcidev, reg, &val);
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return (val >> shift) & 0xf;
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}
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static unsigned long __sizeram(void)
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{
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unsigned long totalmem;
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unsigned char bank, mem, prevmem;
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u8 sma_status, sma_size, sma_size_bits;
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// fixed so tha banks 56 & 57 are looked at as well.
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unsigned long firstbank = 0x5a, lastbank = 0x61;
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u8 sma_status, sma_size_bits;
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struct pci_dev *pcidev;
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unsigned long memtop, highest, size, sma_size;
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int bank, i;
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static const unsigned char ma_table[] = {0, 8, 0xe};
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unsigned char ma_tmp, val;
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extern void cache_enable(void), cache_disable(void);
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pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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if (! pcidev)
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return 0;
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/* In assembly part, we have initialized all RAM chips,
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* brought the first equipped RAM bank to address zero,
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* and set correct MA mapping type of that bank.
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* Now, we have to detect the size of the first bank,
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* then configure rest of banks. */
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/* Cache must be disabled to detect the RAM. */
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cache_disable();
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/* Find the first bank configured by assembly part. */
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for (bank = 0; bank < 6; bank++) {
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pci_read_config_byte(pcidev, 0x5a + bank, &val);
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if (val != 0)
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break;
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}
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memtop = find_size(0, 1024*1024);
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memtop &= ~0x7fffff; /* Unit of 8MB */
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printk_info("Bank%d %dMB (MA type 0x%x)\n", bank,
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memtop>>20, get_ma_mapping(pcidev, bank));
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pci_write_config_byte(pcidev, 0x5a + bank, memtop>>23);
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for (bank++; bank < 6; bank++) {
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if (bank & 1) {
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/* We don't change MA mapping of this bank
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* since it is shared with the previous bank.
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* Most possibly this is the other side of a
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* double-sided DIMM. */
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size = find_size(memtop, 0);
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size &= ~0x7fffff;
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if (size) {
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printk_info("Bank%d %dMB\n", bank, size>>20);
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memtop += size;
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}
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} else {
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/* Try MA mapping types and find the one which gives
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* highest address without wrap-around.
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* It should be the correct mapping for the DIMM,
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* and the returned address is the size of the DIMM. */
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highest = 0;
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ma_tmp = 0;
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for (i = 0; i < sizeof(ma_table)/sizeof(ma_table[0]); i++) {
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set_ma_mapping(pcidev, bank, ma_table[i]);
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size = find_size(memtop, 0);
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printk_debug("bank %d MA 0x%x: %d bytes\n",
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bank, ma_table[i], size);
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if (size > highest) {
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highest = size;
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ma_tmp = ma_table[i];
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}
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}
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highest &= ~0x7fffff;
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if (highest) {
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printk_info("Bank%d %dMB (MA type 0x%x)\n",
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bank, highest>>20, ma_tmp);
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memtop += highest;
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}
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set_ma_mapping(pcidev, bank, ma_tmp);
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}
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pci_write_config_byte(pcidev, 0x5a + bank, memtop>>23);
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}
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/* As well as 6 bank registers above, it seems we have to fill
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* these 2 registers. */
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pci_write_config_byte(pcidev, 0x56, memtop>>23);
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pci_write_config_byte(pcidev, 0x57, memtop>>23);
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cache_enable();
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/* Frame buffer size */
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// Documentation on VT8601 - Pg 51 Rev 1.3 Sept 1999 says
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// Device 0 Offset FB - Frame buffer control
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// bit
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@ -35,41 +177,31 @@ static unsigned long __sizeram(void)
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pci_read_config_byte(pcidev, 0xfb, &sma_status);
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sma_size_bits = (sma_status >> 4) & 0x03;
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if (sma_size_bits > 0)
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sma_size = 0x01 << sma_size_bits;
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sma_size = (1024*1024) << sma_size_bits;
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else
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sma_size = 0;
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for(totalmem = mem = prevmem = 0, bank = firstbank;
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bank <= lastbank; bank++) {
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// last 2 banks are in regs before first bank so
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// wrap round if > 0x5f
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unsigned long rbank = (bank > 0x5f) ? bank - 10 : bank;
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printk_info("Total %dMB + frame buffer %dMB\n",
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(memtop - sma_size)>>20, sma_size>>20);
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pci_read_config_byte(pcidev, rbank, &mem);
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/* Turn on shadow DRAM at 0xC0000-0xFFFFF so we can write
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* PIRQ table, VGA BIOS, Bochs BIOS, etc. */
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printk_debug("Enabling shadow DRAM at 0xC0000-0xFFFFF: ");
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pci_write_config_byte(pcidev, 0x61, 0xff);
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pci_write_config_byte(pcidev, 0x62, 0xff);
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pci_write_config_byte(pcidev, 0x63, 0xf0);
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printk_debug("done\n");
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// sanity check. If the mem value is < prevmem,
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// that is an error, so skip this step.
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if (mem < prevmem) {
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printk_err("ERROR: bank 0x%x, mem 0x%x TOO SMALL\n",
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rbank, prevmem);
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printk_err("Should be >= 0x%x\n", prevmem);
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} else
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totalmem += (mem - prevmem) * 8;
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prevmem = mem;
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}
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totalmem -= sma_size;
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totalmem *= 1024;
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return totalmem;
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return (memtop - sma_size) >> 10; // return in kilo bytes
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}
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struct mem_range *sizeram(void)
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{
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static struct mem_range mem[3];
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mem[0].basek = 0;
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mem[0].sizek = 640;
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mem[1].basek = 1024;
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mem[1].basek = 768;
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mem[1].sizek = __sizeram();
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mem[2].basek = 0;
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mem[2].sizek = 0;
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@ -77,19 +209,27 @@ struct mem_range *sizeram(void)
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mem[1].sizek = 64*1024;
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}
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mem[1].sizek -= mem[1].basek;
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return &mem;
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return mem;
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}
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#ifdef HAVE_FRAMEBUFFER
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void framebuffer_on()
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{
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#if 0 /* This code has not been working (always reads 0xffff)
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* and I still can bring up VGA (with original VGA BIOS under ADLO)
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* after disabling this. -- ts1 */
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unsigned long devfn;
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u16 command;
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devfn = PCI_DEVFN(0, 1);
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pcibios_read_config_word(0, devfn, 0x3e, &command);
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command |= 0x08;
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//command |= 0x08;
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command |= 0x0c;
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pcibios_write_config_word(0, devfn, 0x3e, command);
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printk_debug("wrote %02x\n", command);
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pcibios_read_config_word(0, devfn, 0x3e, &command);
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printk_debug("readback %02x\n", command);
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#endif
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}
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#endif
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@ -25,52 +25,92 @@ it with the version available from LANL.
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* correctly - at least on my VIA epia motherboard. 64MB DIMM in slot 0.
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*/
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#define loop200 $0x5000
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#define loop100 $0x2500
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/* Added automatic detection of first equipped bank and its MA mapping type.
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* (Rest of configuration is done in C)
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* 5/19/03 by SONE Takeshi <ts1@tsn.or.jp>
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*/
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// Set to 1 if your DIMMs are PC133
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// Note that I'm assuming CPU's FSB frequency is 133MHz. If your CPU runs
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// at another bus speed, you might need to change some of register values.
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#ifndef DIMM_PC133
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#define DIMM_PC133 0
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#endif
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// Set to 1 if your DIMMs are CL=2
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#ifndef DIMM_CL2
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#define DIMM_CL2 0
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#endif
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/* Stable ~1 usec delay by hitting unused ISA port. */
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#define UDELAY(x) movl $x,%ecx; 9: outb %al,$0x81; loop 9b
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#define DIMMS_READ(x) \
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movl 0x00000000+x, %eax; \
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movl 0x10000000+x, %eax; \
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movl 0x20000000+x, %eax; \
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movl 0x30000000+x, %eax; \
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movl 0x40000000+x, %eax; \
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movl 0x50000000+x, %eax
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#define DIMMS_WRITE(x) \
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movl %eax, 0x00000000+x; \
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movl %eax, 0x10000000+x; \
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movl %eax, 0x20000000+x; \
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movl %eax, 0x30000000+x; \
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movl %eax, 0x40000000+x; \
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movl %eax, 0x50000000+x
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raminit:
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intel_chip_post_macro(0x35)
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/*; new code... pulled from via stuff.*/
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/* initialize registers */
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// memory clk enable. We are not using ECC
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CS_WRITE($0x78, $0x01)
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// dram control, see the book.
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CS_WRITE($0x68, $0x42)
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#if DIMM_PC133
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CS_WRITE($0x68, $0x52)
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#else
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CS_WRITE($0x68, $0x42)
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#endif
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// dram control, see the book.
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CS_WRITE($0x6B, $0x0d)
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// 64/128 MB dram
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CS_WRITE($0x58, $0x80)
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// 64/128 MB dram
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CS_WRITE($0x59, $0x00)
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// bank 0 ends at 64 MB
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CS_WRITE($0x5A, $0x08)
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// bank 1 ends at 64 MB
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CS_WRITE($0x5B, $0x08)
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// bank 2 ends at 64 MB
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CS_WRITE($0x5C, $0x08)
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// bank 2 ends at 64 MB
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CS_WRITE($0x5D, $0x08)
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// bank 2 ends at 64 MB
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CS_WRITE($0x5E, $0x08)
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// bank 2 ends at 64 MB
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CS_WRITE($0x5F, $0x08)
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CS_WRITE($0x6B, $0x0c)
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// Initial setting, 256MB in each bank, will be rewritten later.
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CS_WRITE($0x5A, $0x20)
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CS_WRITE($0x5B, $0x40)
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CS_WRITE($0x5C, $0x60)
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CS_WRITE($0x5D, $0x80)
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CS_WRITE($0x5E, $0xA0)
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CS_WRITE($0x5F, $0xC0)
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// It seems we have to take care of these 2 registers as if
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// they are bank 6 and 7.
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CS_WRITE($0x56, $0xC0)
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CS_WRITE($0x57, $0xC0)
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// SDRAM in all banks
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CS_WRITE($0x60, $0x3F)
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// DRAM timing. I'm suspicious of this
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// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
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// ras precharge 4T, RAS pulse 5T, CAS 2T
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// as per the note below, we change to cas 3 2000/8/31
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// ras precharge 4T, RAS pulse 5T
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// cas2 is 0xd6, cas3 is 0xe6
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// we're also backing off write pulse width to 2T, so result is 0xee
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CS_WRITE($0x64, $0xe6)
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CS_WRITE($0x65, $0x95)
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CS_WRITE($0x66, $0x95)
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#if DIMM_CL2
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CS_WRITE($0x64, $0xd4)
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CS_WRITE($0x65, $0xd4)
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CS_WRITE($0x66, $0xd4)
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#else // CL=3
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CS_WRITE($0x64, $0xe4)
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CS_WRITE($0x65, $0xe4)
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CS_WRITE($0x66, $0xe4)
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#endif
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// dram frequency select. We set 66/66.
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// no 256 m, enable 4K pages for 64M dram.
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CS_WRITE($0x69, $0xac)
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// dram frequency select.
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// enable 4K pages for 64M dram.
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#if DIMM_PC133
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CS_WRITE($0x69, $0x3c)
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#else
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CS_WRITE($0x69, $0xac)
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#endif
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// refresh counter, disabled.
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CS_WRITE($0x6A, $0x00)
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// clkenable configuration. kevinh FIXME - add precharge
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@ -80,102 +120,188 @@ raminit:
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// As per Cindy Lee, set to 0x37, not 0x57
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CS_WRITE($0x6D, $0x7f)
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/* Initialize all banks at once */
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/* begin to initialize*/
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// I forget why we need this, but we do
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mov $0xa55a5aa5, %eax
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mov %eax, 0
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mov %eax, 0x4000000
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DIMMS_WRITE(0)
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/* set NOP*/
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CS_WRITE($0x6C, $0x01)
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/* wait 200us*/
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// You need to do the memory reference. That causes the nop cycle.
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop200)
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DIMMS_READ(0)
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UDELAY(400)
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/* set precharge */
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CS_WRITE($0x6C, $0x02)
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/* dummy reads*/
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mov 0x0, %eax
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mov 0x4000000, %eax
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DIMMS_READ(0)
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UDELAY(200)
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/* set CBR*/
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CS_WRITE($0x6C, $0x04)
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/* do 8 reads and wait 100us between each - from via*/
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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mov 0x0, %eax
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mov 0x4000000, %eax
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DELAY(loop100)
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/* do 8 reads and wait >100us between each - from via*/
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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||||
DIMMS_READ(0)
|
||||
UDELAY(200)
|
||||
|
||||
/* set MRS*/
|
||||
// 0x150 is cas2. We are now using 0x1d0, which is cas3
|
||||
CS_WRITE($0x6c, $0x03)
|
||||
movl $0x1d0, %ecx
|
||||
movl (%ecx), %eax
|
||||
movl $0x40001d0, %ecx
|
||||
movl (%ecx), %eax
|
||||
#if DIMM_CL2
|
||||
DIMMS_READ(0x150)
|
||||
#else // CL=3
|
||||
DIMMS_READ(0x1d0)
|
||||
#endif
|
||||
UDELAY(200)
|
||||
|
||||
/* set to normal mode */
|
||||
CS_WRITE($0x6C, $0x08)
|
||||
movl $0x55aa55aa, %eax
|
||||
mov %eax, 0x0
|
||||
mov 0x0, %eax
|
||||
DIMMS_WRITE(0)
|
||||
DIMMS_READ(0)
|
||||
UDELAY(200)
|
||||
|
||||
// Set the refresh rate.
|
||||
#if DIMM_PC133
|
||||
CS_WRITE($0x6A, $0x86)
|
||||
#else
|
||||
CS_WRITE($0x6A, $0x65)
|
||||
#endif
|
||||
// enable multi-page open
|
||||
CS_WRITE($0x6B, $0x01)
|
||||
CS_WRITE($0x6B, $0x0d)
|
||||
|
||||
|
||||
/* From Mike Fan:
|
||||
Hi all:
|
||||
If you are porting PM133, then you have to set DRAM Row Ending Address.
|
||||
You did not set Rx56 and Rx57 in intel_pm133ram.S.
|
||||
That register setting is like Rx5A~Rx5F.
|
||||
Maybe could fix the mem wrapping issue.
|
||||
(from Ron Minnich)
|
||||
My manual says these are non-cacheable region registers.
|
||||
(Turns out the manual is wrong. However, this did not help.
|
||||
2000/8/31 8:49 am I am setting all dram to cas3, and if that fails,
|
||||
I'll be trying some of Cindy's other recommendations.
|
||||
DRAM is currently CAS2. Symptom is an explosion in free_all_bootmem_core,
|
||||
In the loop where it is freeing bootmem alloc pages from low mem.
|
||||
2000/8/31: 10:57 No change, Linux still crashes. We'll try Cindy Lee's recommendation
|
||||
RE Register 0x6d, set it to 0x37. All our other settings conform to her
|
||||
other recommendations. We also need to see whether we should be setting
|
||||
Fixed MTRRs, but that seems unlikely.
|
||||
2000/8/31: 5:56 PM. No significant change. We're going to try to use 1 cycle writes
|
||||
instead of 2. None of this feels like it is the real problem. Fixed MTRRs
|
||||
helped a tiny bit. We can get to schedule() before we crash, but only
|
||||
if we set a breakpoint after the first loop in free_all_bootmem_core
|
||||
*/
|
||||
CS_WRITE($0x56, $0x10)
|
||||
CS_WRITE($0x57, $0x10)
|
||||
/* Begin auto-detection
|
||||
* Find the first bank with DIMM equipped. */
|
||||
|
||||
/* Maximum possible memory in bank 0, none in other banks.
|
||||
* Starting from bank 0, we's fill 0 in these registers
|
||||
* until memory is found. */
|
||||
CS_WRITE($0x5A, $0xff)
|
||||
CS_WRITE($0x5B, $0xff)
|
||||
CS_WRITE($0x5C, $0xff)
|
||||
CS_WRITE($0x5D, $0xff)
|
||||
CS_WRITE($0x5E, $0xff)
|
||||
CS_WRITE($0x5F, $0xff)
|
||||
CS_WRITE($0x56, $0xff)
|
||||
CS_WRITE($0x57, $0xff)
|
||||
|
||||
movl $0x5A, %ebx // first bank
|
||||
1:
|
||||
/* Write different values to 0 and 8, then read from 0.
|
||||
* If values of address 0 match, we have something there. */
|
||||
movl $0x12345678, %eax
|
||||
movl %eax, 0
|
||||
movl $0x87654321, %edx
|
||||
movl %edx, 8
|
||||
movl 0, %edx
|
||||
cmpl %eax, %edx
|
||||
je 2f
|
||||
/* No memory in this bank. Tell it to the bridge. */
|
||||
movl %ebx, %eax
|
||||
xorl %edx, %edx
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
incl %ebx
|
||||
cmpl $0x60, %ebx
|
||||
jne 1b
|
||||
/* No memory at all! */
|
||||
CONSOLE_EMERG_TX_STRING($msg_nomem)
|
||||
1:
|
||||
hlt
|
||||
jmp 1b
|
||||
2:
|
||||
|
||||
/* Detect MA mapping type of the first bank. */
|
||||
|
||||
jmp raminit_ma
|
||||
raminit_ma_reg_table:
|
||||
/* Values for MA type register to try */
|
||||
.word 0x0000, 0x8088, 0xe0ee
|
||||
.word 0xffff // end mark
|
||||
|
||||
raminit_ma:
|
||||
xorl %esi, %esi // highest address
|
||||
movl $raminit_ma_reg_table, %ebx
|
||||
1:
|
||||
movw (%ebx), %cx
|
||||
cmpw $0xffff, %cx
|
||||
je raminit_ma_done
|
||||
movl $0x58, %eax
|
||||
PCI_WRITE_CONFIG_WORD
|
||||
|
||||
xorl %eax, %eax
|
||||
movl %eax, (%eax)
|
||||
|
||||
// Write to addresses with only one address bit on,
|
||||
// from 0x80000000 to 0x00000008 (lower 3 bits are ignored, assuming
|
||||
// 64-bit bus).
|
||||
// Then what is read at address 0 is the value written to the lowest
|
||||
// address where it gets wrap-around. That address is either the size
|
||||
// of the bank, or a missing bit due to incorrect MA mapping.
|
||||
movl $0x80000000, %eax
|
||||
2:
|
||||
movl %eax, (%eax)
|
||||
shrl $1, %eax
|
||||
cmpl $4, %eax
|
||||
jne 2b
|
||||
|
||||
movl 0, %eax
|
||||
cmpl %eax, %esi
|
||||
jnc 3f
|
||||
|
||||
// This is the current best MA mapping.
|
||||
// Save the address and its MA mapping value.
|
||||
movl %eax, %esi
|
||||
movl %ecx, %edi
|
||||
3:
|
||||
incl %ebx
|
||||
incl %ebx
|
||||
jmp 1b
|
||||
|
||||
|
||||
raminit_ma_done:
|
||||
// Set the best (hopefully correct) MA mapping type.
|
||||
movl $0x58, %eax
|
||||
movl %edi, %ecx
|
||||
PCI_WRITE_CONFIG_WORD
|
||||
|
||||
CONSOLE_DEBUG_TX_STRING($msg_enabled)
|
||||
CONSOLE_DEBUG_TX_HEX32(%esi)
|
||||
CONSOLE_DEBUG_TX_STRING($msg_bytes)
|
||||
|
||||
/*
|
||||
* We have the size of first bank in %esi, but throwing it away.
|
||||
* Sizing will again be done in C, because we'll configure the rest
|
||||
* of banks in there anyway.
|
||||
*/
|
||||
|
||||
//CALLSP(dumpnorth)
|
||||
|
||||
intel_chip_post_macro(0x36)
|
||||
|
||||
|
||||
.section ".rom.data"
|
||||
msg_nomem:
|
||||
.asciz "No memory\r\n"
|
||||
msg_enabled:
|
||||
.asciz "Enabled first bank of RAM: 0x"
|
||||
msg_bytes:
|
||||
.asciz " bytes\r\n"
|
||||
.previous
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue