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fsp_broadwell_de: Enable Super I/O address range decode

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If there is an external 16550 like UART, one needs to enable
the appropriate address ranges before console_init() is called
so that the init sequence can reach the external UART. Otherwise
the UART will only start working in ramstage and will produce
unreadable characters in romstage due to the lack of initialization.

Tested-on: Siemens MC_BDX1

Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15495
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Werner Zeh 2016-06-29 07:17:21 +02:00
parent 66c20c4dfa
commit 61f4b42f2c
2 changed files with 10 additions and 1 deletions
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4
src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
View file

@ -21,6 +21,8 @@
#define REVID 0x08
#define PIRQ_RCR1 0x60
#define PIRQ_RCR2 0x68
#define LPC_IO_DEC 0x80
#define LPC_EN 0x82
#define GEN_PMCON_1 0xA0
#define GEN_PMCON_2 0xA2
#define GEN_PMCON_3 0xA4
@ -83,4 +85,4 @@
#define TCO_TMR_HALT (1 << 11)
#define TCO_TMR 0x70
#endif /* _SOC_LPC_H_ */
#endif /* _SOC_LPC_H_ */

7
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
View file

@ -48,6 +48,13 @@ static void init_rtc(void)
void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
{
post_code(0x40);
if (!IS_ENABLED(CONFIG_INTEGRATED_UART)) {
/* Enable decoding of I/O locations for Super I/O devices */
pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
LPC_IO_DEC, 0x0010);
pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
LPC_EN, 0x340f);
}
console_init();
init_rtc();