mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
LPC serial IRQs were being left enabled when there is no LPC serial device.
Signed-off-by: Marc Jones <marcj303@yahoo.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@986 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
parent
c49f41d946
commit
607e6aff43
1 changed files with 2 additions and 2 deletions
|
@ -34,9 +34,9 @@
|
|||
/config/("southbridge/amd/cs5536/dts");
|
||||
/* Interrupt enables for LPC bus.
|
||||
* Each bit is an IRQ 0-15. */
|
||||
lpc_serirq_enable = "0x0000105A";
|
||||
lpc_serirq_enable = "0x00001002";
|
||||
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
|
||||
lpc_serirq_polarity = "0x0000EFA5";
|
||||
lpc_serirq_polarity = "0x0000EFFD";
|
||||
/* 0:continuous 1:quiet */
|
||||
lpc_serirq_mode = "1";
|
||||
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
|
||||
|
|
Loading…
Add table
Reference in a new issue