RLX 800i support

This commit is contained in:
Ronald G. Minnich 2002-05-28 23:29:17 +00:00
parent 2ce191a0ed
commit 5fbdd5eabe
10 changed files with 1429 additions and 1094 deletions

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@ -1,33 +1,35 @@
arch i386 arch i386
mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc mainboardinit cpu/i386/entry32.inc
ldscript cpu/i386/entry16.lds ldscript cpu/i386/entry16.lds
ldscript cpu/i386/entry32.lds ldscript cpu/i386/entry32.lds
mainboardinit cpu/i386/reset16.inc mainboardinit cpu/i386/reset16.inc
ldscript cpu/i386/reset16.lds ldscript cpu/i386/reset16.lds
mainboardinit northbridge/micron/21PAD/reset_test.inc mainboardinit northbridge/micron/21PAD/chipset_init.inc
mainboardinit superio/acer/m1535/setup_serial.inc
# mainboardinit pc80/serial.inc
# Inspired by the cache as ram testing... mainboardinit arch/i386/lib/console.inc
#
biosbase 0xffff0000
rambase 0x00000800
option XIP_ROM_BASE=0xffff0000
option XIP_ROM_SIZE=0x10000
option STACK_SIZE=0x2000
#SUPERIO
option SERIAL_SUPERIO_BASEADDRESS=0x3f0
#option HAVE_PIRQ_TABLE=1
northbridge micron/21PAD northbridge micron/21PAD
southbridge acer/m1535 southbridge acer/m1535
mainboardinit cpu/p6/earlymtrr.inc superio acer/m1535
option ENABLE_FIXED_AND_VARIABLE_MTRRS mainboardinit cpu/p6/earlymtrr.inc
mainboardinit ram/dump_northbridge2.inc
mainboardinit ram/ramtest.inc
#mainboardinit mainboard/digitallogic/smartcore-p5/do_ramtest.inc
#mainboardinit northbridge/micron/21PAD/reset_test.inc
#option ENABLE_FIXED_AND_VARIABLE_MTRRS
option NO_KEYBOARD option NO_KEYBOARD
option ZKERNEL_START=0xfff40000 option ZKERNEL_START=0xfffc0000
option ZKERNEL_MASK=0x3ed option ZKERNEL_MASK=0xff
option HAVE_PIRQ_TABLE=1 option HAVE_PIRQ_TABLE=1
object mainboard.o object mainboard.o
@ -36,3 +38,13 @@ object irq_tables.o HAVE_PIRQ_TABLE
cpu p6 cpu p6
cpu p5 cpu p5
#
# Inspired by the cache as ram testing...
#
#
#biosbase 0xffff0000
#rambase 0x00000800
#option XIP_ROM_BASE=0xffff0000
#option XIP_ROM_SIZE=0x10000
#option STACK_SIZE=0x2000
#OPTION RAM_TEST

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@ -0,0 +1,406 @@
/************************************
* FILE: src/northbridge/micron/21PAD/chipset_init.inc
* NAME: Suravee Suthikulpanit
* suravee@lanl.gov
* 5/2002
*
* This is the RLX 800i initialization for:
* - Micron 21PAD Fn 0,1
* - Acer M1535
*************************************/
#define PM_DEVFN CONFIG_ADDR(0, 0, 0)
.type chipsetinit_start, @function
jmp chipsetinit_start
/* table of settings for initial registers */
/* format is register #, and value, OR value */
#if 0
// Original Table from the book
register_table:
.byte 0x04, 0x00, 0x00
.byte 0x05, 0x00, 0x00
.byte 0x07, 0x70, 0x70
.byte 0x0c, 0x04, 0x04
.byte 0x0d, 0x40, 0x40
.byte 0x40, 0x07, 0x07
.byte 0x41, 0x00, 0x00
.byte 0x42, 0x00, 0x00
.byte 0x43, 0x00, 0x00
.byte 0x4c, 0x03, 0x03
.byte 0x4d, 0x00, 0x00
.byte 0x4e, 0x40, 0x40
.byte 0x50, 0x94, 0x94
.byte 0x52, 0x01, 0x01
.byte 0x53, 0x01, 0x01
.byte 0x5c, 0x00, 0x00
.byte 0x5d, 0x00, 0x00
.byte 0x5e, 0x00, 0x00
.byte 0x5f, 0x00, 0x00
.byte 0x60, 0x00, 0x00
.byte 0x61, 0x00, 0x00
.byte 0x62, 0x00, 0x00
.byte 0x63, 0x00, 0x00
.byte 0x64, 0x00, 0x00
.byte 0x65, 0x00, 0x00
.byte 0x66, 0x00, 0x00
.byte 0x67, 0x00, 0x00
.byte 0x68, 0x00, 0x00
.byte 0x69, 0x00, 0x00
.byte 0x6a, 0x00, 0x00
.byte 0x6b, 0x00, 0x00
.byte 0x6c, 0x00, 0x00
.byte 0x6d, 0x00, 0x00
.byte 0x6e, 0x00, 0x00
.byte 0x6f, 0x00, 0x00
.byte 0x70, 0xb8, 0xb8
.byte 0x71, 0x8f, 0x8f
.byte 0x72, 0x3f, 0x3f
.byte 0x73, 0x79, 0x79
.byte 0x74, 0x00, 0x00
.byte 0x75, 0x00, 0x00
.byte 0x76, 0x00, 0x00
.byte 0x77, 0x00, 0x00
.byte 0x78, 0x00, 0x00
.byte 0x79, 0x00, 0x00
.byte 0x7a, 0x00, 0x00
.byte 0x7b, 0x00, 0x00
.byte 0x8c, 0xf4, 0xf4
.byte 0x8d, 0x82, 0x82
.byte 0x8e, 0x9c, 0x9c
.byte 0x8f, 0xc0, 0xc0
.byte 0x90, 0x00, 0x00
.byte 0x91, 0x00, 0x00
.byte 0x92, 0x00, 0x00
.byte 0x93, 0x00, 0x00
.byte 0x94, 0x00, 0x00
.byte 0xa0, 0x00, 0x00
.byte 0xa1, 0x00, 0x00
.byte 0xa2, 0x00, 0x00
.byte 0xc0, 0x00, 0x00
.byte 0xc1, 0x00, 0x00
.byte 0xc2, 0x00, 0x00
.byte 0xc3, 0xc2, 0xc2
.byte 0xc8, 0x47, 0x47
.byte 0xc9, 0xfb, 0xfb
.byte 0xca, 0x00, 0x00
.byte 0xcb, 0x00, 0x00
.byte 0xd6, 0x00, 0x00
.byte 0xd7, 0x00, 0x00
.byte 0xe0, 0x7f, 0x7f
.byte 0xe2, 0x00, 0x00
.byte 0xf0, 0x30, 0x30
.byte 0xf1, 0x00, 0x00
.byte 0xf2, 0x00, 0x00
.byte 0x0 /* end of table */
#else
// HOST-PCI Bridge Controler
// Modified table
register_table:
.byte 0x04, 0x00, 0x00
.byte 0x05, 0x00, 0x00
.byte 0x07, 0x70, 0x70
.byte 0x0c, 0x04, 0x04
.byte 0x0d, 0x40, 0x40
.byte 0x40, 0x07, 0x07
.byte 0x41, 0x00, 0x00
.byte 0x42, 0x00, 0x00
.byte 0x43, 0x00, 0x00
.byte 0x4c, 0x03, 0x03
.byte 0x4d, 0x00, 0x00
.byte 0x4e, 0x40, 0x40
.byte 0x50, 0x94, 0x94
.byte 0x52, 0x01, 0x01
.byte 0x53, 0x01, 0x01
// PCI0 bus device control
.byte 0x54, 0x00, 0x00
.byte 0x55, 0x00, 0x00
.byte 0x56, 0x10, 0x10
.byte 0x57, 0x01, 0x01
.byte 0x5c, 0x00, 0x00
.byte 0x5d, 0x00, 0x00
.byte 0x5e, 0x00, 0x00
.byte 0x5f, 0x00, 0x00
.byte 0x60, 0x00, 0x00
.byte 0x61, 0x00, 0x00
.byte 0x62, 0x00, 0x00
.byte 0x63, 0x00, 0x00
// Host-PCI I/O Range
.byte 0x64, 0x00, 0x00
.byte 0x65, 0x00, 0x00
.byte 0x66, 0xff, 0xff
.byte 0x67, 0x0f, 0x0f
.byte 0x68, 0x00, 0x00
.byte 0x69, 0x00, 0x00
.byte 0x6a, 0xff, 0xff
.byte 0x6b, 0x0f, 0x0f
.byte 0x6c, 0x00, 0x00
.byte 0x6d, 0x00, 0x00
.byte 0x6e, 0x00, 0x00
.byte 0x6f, 0x00, 0x00
.byte 0x70, 0xb8, 0xb8
.byte 0x71, 0x8f, 0x8f
.byte 0x72, 0x3f, 0x3f
.byte 0x73, 0x79, 0x79
.byte 0x74, 0x00, 0x00
.byte 0x75, 0x00, 0x00
.byte 0x76, 0x00, 0x00
.byte 0x77, 0x00, 0x00
.byte 0x78, 0x00, 0x00
.byte 0x79, 0x00, 0x00
.byte 0x7a, 0x00, 0x00
.byte 0x7b, 0x00, 0x00
.byte 0x8c, 0xf4, 0xf4
.byte 0x8d, 0x82, 0x82
.byte 0x8e, 0x9c, 0x9c
.byte 0x8f, 0xc0, 0xc0
.byte 0x90, 0x00, 0x00
.byte 0x91, 0x00, 0x00
.byte 0x92, 0x00, 0x00
.byte 0x93, 0x00, 0x00
.byte 0x94, 0x00, 0x00
// Switch control
.byte 0xa0, 0x5b, 0x5b
.byte 0xa1, 0x36, 0x36
.byte 0xa2, 0x04, 0x04
// PCI Arbiter Control
.byte 0xc0, 0x00, 0x00
.byte 0xc1, 0x00, 0x00
.byte 0xc2, 0x02, 0x02
.byte 0xc3, 0x42, 0x42
.byte 0xc8, 0x47, 0x47
.byte 0xc9, 0xfb, 0xfb
.byte 0xca, 0x00, 0x00
.byte 0xcb, 0x00, 0x00
.byte 0xd6, 0x00, 0x00
.byte 0xd7, 0x00, 0x00
.byte 0xe0, 0x7f, 0x7f
.byte 0xe2, 0x00, 0x00
// PCI Master Control
.byte 0xf0, 0xfc, 0xfc
.byte 0xf1, 0x02, 0x02
.byte 0xf2, 0x00, 0x00
.byte 0x0 /* end of table */
#endif
// Original Table from the book
// Memory Controler Table
register_table1:
.byte 0x0c, 0xff, 0xff
.byte 0x0d, 0x40, 0x40
.byte 0x2f, 0x40, 0x10 // Subsytem Vendor ID
.byte 0x2e, 0x40, 0x42 // !!! Try this
.byte 0x2d, 0x40, 0x10
.byte 0x2c, 0x40, 0x42
.byte 0x40, 0x00, 0x00
.byte 0x41, 0x01, 0x01 // !!!!! Design specific
.byte 0x42, 0x00, 0x00
.byte 0x43, 0x00, 0x00
.byte 0x44, 0x00, 0x02
.byte 0x48, 0x00, 0x00
.byte 0x8c, 0x00, 0x08 // ECC Control
.byte 0x8d, 0x00, 0x89 // Symmetric Select and Config
.byte 0x8e, 0x10, 0x10 // !!!!! 780d
.byte 0x8f, 0x04, 0x04
.byte 0x92, 0x02, 0x02 // Error Status/Command
.byte 0xa0, 0x00, 0x00
.byte 0xa1, 0x43, 0x43
.byte 0xa2, 0x3f, 0x3f
.byte 0xa3, 0x92, 0x92
.byte 0xc8, 0x94, 0x94 // !!!!! NOT SURE
.byte 0xc9, 0x49, 0x49
.byte 0xca, 0x35, 0x35
.byte 0xcb, 0x6d, 0x6d
.byte 0xe0, 0x80, 0x80
.byte 0xf0, 0x00, 0x00
.byte 0xf1, 0x00, 0x00
.byte 0xf2, 0x00, 0x00
.byte 0xf3, 0x00, 0x00
.byte 0xf4, 0x00, 0x00
.byte 0xf5, 0x00, 0x00
.byte 0xf6, 0x00, 0x00
.byte 0xf7, 0x00, 0x00
.byte 0xf8, 0x00, 0x00
.byte 0xf9, 0x00, 0x00
.byte 0xfa, 0x00, 0x00
.byte 0xfb, 0x00, 0x00
.byte 0xfc, 0x00, 0x00
.byte 0xfd, 0x00, 0x00
.byte 0xfe, 0x00, 0x00
.byte 0xff, 0x00, 0x00
.byte 0x0 /* end of table */
#if 0
// Original Table from the book
m1535_table:
.byte 0x61, 0xd0, 0x00 // Set Keyboard Cntrl to be internal
.byte 0x41, 0x23, 0x23
.byte 0x42, 0x08, 0x08
.byte 0x43, 0x85, 0x85
.byte 0x47, 0x07, 0x07
.byte 0x58, 0x5c, 0x5c
.byte 0x72, 0x0b, 0x0b
.byte 0x77, 0x36, 0x36
.byte 0x0 // end of m1535_table
m7101_table:
.byte 0xda, 0x40, 0x40
.byte 0xe0, 0x00, 0x00
.byte 0xe1, 0x40, 0x40
.byte 0xe2, 0x00, 0x00 // SMB base addr (low)
.byte 0xe3, 0x50, 0x50 // SMB base addr (high)
.byte 0x80, 0x06, 0x06
.byte 0x83, 0x02, 0x02
.byte 0xd1, 0x06, 0x06
.byte 0xf0, 0x01, 0x01
.byte 0xf2, 0x20, 0x20
.byte 0x0 // end of m7101_table
#endif
// Ron's table
m1535_table:
.byte 0x58, 0x00, 0x4c // enable IDE controller
.byte 0x44, 0x00, 0x1d // set edge mode, primary channel IRQ 14
// for IDE 1
.byte 0x47, 0xff, 0x40 // enable flash rom r/w
.byte 0x41, 0x00, 0x0d // enable superIO recovery
.byte 0x0 // end of m1535_table
m7101_table:
.byte 0xe2, 0x00, 0x00 // SMB base addr (low)
.byte 0xe3, 0x50, 0x50 // SMB base addr (high)
.byte 0x80, 0x3e, 0x3e //
.byte 0xd1, 0x46, 0x46 // SMB IO space enable
.byte 0xf0, 0x01, 0x01 // SMB Host config
.byte 0xb8, 0x40, 0x40 // GPOs
.byte 0x0 // end of m7101_table
//--------------------------------------
chipsetinit_start:
// RESET CONTROL
// - This reset the host controller
// and memory interface
// Fn 0 offset D4 : set to 0xe0 and back to 0x0
xorl %eax, %eax
xorl %edx, %edx
movl $0x0000c000, %eax // Northbridge is dev 18 << 3 + 0 = 0xC0
movb 0xe0, %dl
PCI_WRITE_CONFIG_BYTE
movb 0x00, %dl
PCI_WRITE_CONFIG_BYTE
/* standard x86 loop on table until done code */
/* assumes that: devfn is 0 (safe on anything we've seen) */
/* which means addresses are a byte */
/* address is first, then data */
/* NOTE: read returns result in %al */
/* WRITE expects write value in %dl, address in %al */
// BEGIN NORTHBRIDGE INIT
movl $register_table, %esi
1:
xorl %edx, %edx // clear edx
//xorl %eax, %eax // clear eax
movl $0x0000c000, %eax // Northbridge is dev 18 << 3 + 0 = 0xC0
movb (%esi), %cl /* save the address (register #) in %cl */
movb %cl, %al
testb %al, %al // 0 means end of chipset init
jz done_chipset_init
PCI_READ_CONFIG_BYTE
movb %al, %dl
inc %esi
andb (%esi), %dl
inc %esi
orb (%esi), %dl
mov %cl, %al
PCI_WRITE_CONFIG_BYTE
inc %esi
jmp 1b
done_chipset_init:
northbridge_fn1_start:
movl $register_table1, %esi
1:
xorl %edx, %edx // clear edx
movl $0x0000c100, %eax // Northbridge is dev 18 << 3 + 1 = 0xC1
movb (%esi), %cl /* save the address (register #) in %cl */
movb %cl, %al
testb %al, %al // 0 means end of chipset init
jz done_northbridge_fn1
PCI_READ_CONFIG_BYTE
movb %al, %dl
inc %esi
andb (%esi), %dl
inc %esi
orb (%esi), %dl
mov %cl, %al
PCI_WRITE_CONFIG_BYTE
inc %esi
jmp 1b
done_northbridge_fn1:
m1535_init:
movl $m1535_table, %esi
1:
xorl %edx, %edx
movl $0x00003800, %eax // southbridge is dev 7 << 3 = 0x38
movb (%esi), %cl /* save the address in %cl */
movb %cl, %al
testb %al, %al
jz done_m1535_init
PCI_READ_CONFIG_BYTE
movb %al, %dl
inc %esi
andb (%esi), %dl
inc %esi
orb (%esi), %dl
mov %cl, %al
PCI_WRITE_CONFIG_BYTE
inc %esi
jmp 1b
done_m1535_init:
m7101_init:
movl $m7101_table, %esi
1:
xorl %edx, %edx
//movl $0x00003000, %eax // southbridge is dev 6 << 3 = 0x30
movl $0x00008800, %eax // southbridge is dev 11 << 3 = 0x88
movb (%esi), %cl /* save the address in %cl */
movb %cl, %al
testb %al, %al
jz done_m7101_init
PCI_READ_CONFIG_BYTE
movb %al, %dl
inc %esi
andb (%esi), %dl
inc %esi
orb (%esi), %dl
mov %cl, %al
PCI_WRITE_CONFIG_BYTE
inc %esi
jmp 1b
done_m7101_init:

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@ -10,27 +10,21 @@
const struct irq_routing_table intel_irq_routing_table = { const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*12, /* there can be total 12 devices on the bus */ 32+16*6, /* there can be total 6 devices on the bus */
0, /* Where the interrupt router lies (bus) */ 0, /* Where the interrupt router lies (bus) */
0x90, /* Where the interrupt router lies (dev) */ 0x38, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x10b9, /* Vendor */
0x122e, /* Device */ 0x1533, /* Device */
0, /* Crap (miniport) */ 0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xb9, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 0xe0, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{ {
{0,0x80, {{0x60, 0xdcb8}, {0x65, 0xdcb8}, {0x66, 0xdcb8}, {0x67, 0xdcb8}}, 0x1, 0}, {0,0xa0, {{0x1, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
{0,0x68, {{0x61, 0xdcb8}, {0x66, 0xdcb8}, {0x67, 0xdcb8}, {0x65, 0xdcb8}}, 0x2, 0}, {0,0xc0, {{0, 0xc840}, {0, 0xc840}, {0, 0xc840}, {0, 0xc840}}, 0, 0},
{0,0x60, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, {0,0x48, {{0x2, 0x800}, {0, 0xc840}, {0, 0xc840}, {0, 0xc840}}, 0, 0},
{0,0x58, {{0x62, 0xdcb8}, {0x67, 0xdcb8}, {0x65, 0xdcb8}, {0x66, 0xdcb8}}, 0x3, 0}, {0,0x50, {{0x3, 0x400}, {0, 0xc840}, {0, 0xc840}, {0, 0xc840}}, 0, 0},
{0,0x70, {{0x65, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, {0,0x58, {{0x4, 0x80}, {0, 0xc840}, {0, 0xc840}, {0, 0xc840}}, 0, 0},
{0,0x48, {{0x63, 0xdcb8}, {0x65, 0xdcb8}, {0x66, 0xdcb8}, {0x67, 0xdcb8}}, 0x4, 0}, {0,0x78, {{0, 0xc840}, {0, 0xc840}, {0, 0xc840}, {0, 0xc840}}, 0, 0},
{0,0x90, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x65, 0xdcb8}}, 0, 0},
{0,0xa0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0,0x8, {{0x65, 0xdcb8}, {0x66, 0xdcb8}, {0x67, 0xdcb8}, {0x64, 0xdcb8}}, 0, 0},
{0,0x78, {{0x65, 0xdcb8}, {0x66, 0xdcb8}, {0x67, 0xdcb8}, {0x64, 0xdcb8}}, 0, 0},
{0xff,0x20, {{0x64, 0xdcb8}, {0x65, 0xdcb8}, {0x66, 0xdcb8}, {0x67, 0xdcb8}}, 0x5, 0},
{0xff,0x38, {{0x67, 0xdcb8}, {0x64, 0xdcb8}, {0x65, 0xdcb8}, {0x66, 0xdcb8}}, 0x6, 0},
} }
}; };

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@ -1,8 +1,8 @@
mainboardinit arch/i386/lib/set_memory_size_noop.inc #mainboardinit arch/i386/lib/set_memory_size_noop.inc
mainboardinit northbridge/micron/21PAD/raminit.inc mainboardinit northbridge/micron/21PAD/raminit.inc
mainboardinit sdram/generic_sdram_enable.inc #mainboardinit sdram/generic_sdram_enable.inc
mainboardinit sdram/generic_sdram.inc #mainboardinit sdram/generic_sdram.inc
mainboardinit sdram/generic_zero_ecc_sdram.inc #mainboardinit sdram/generic_zero_ecc_sdram.inc
mainboardinit arch/i386/lib/cpu_reset.inc #mainboardinit arch/i386/lib/cpu_reset.inc
object northbridge.o object northbridge.o

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@ -2,28 +2,71 @@
#include <cpu/p5/io.h> #include <cpu/p5/io.h>
#include <printk.h> #include <printk.h>
void
dumpramregs(struct pci_dev *pcidev)
{
}
unsigned long sizeram() unsigned long sizeram()
{ {
unsigned long totalmem; //unsigned long totalmemKB = 1024*1024;
unsigned char banks; struct pci_dev *pcidev;
unsigned long totalmemKB = 0 ,memfound = 0;
unsigned int datawidth;
unsigned int value,addressingtype;
unsigned int bit4_5, bit2_3,i;
struct pci_dev *pcidev; if((pcidev = pci_find_device(0x1344,0x3321,NULL)) == NULL)
return 0;
/* pci_find_device is way overkill for the host bridge!
* Plus the BX & GX have different device numbers so it
* prevents code sharing.
*/
pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
//pci_read_config_byte(pcidev, 0x67, &banks);
dumpramregs(pcidev); // Read the Rank Type Registers 0-7
// Fn 1 Offset 0x80-0x87
pci_read_config_byte(pcidev,0x80,&value);
return totalmem; for(i=0;(i<=7) && (value != 0);){
// Check addressing type
bit4_5 = value & 0x30;
switch(bit4_5){
case 0 :
addressingtype = 64*1024; //Kb
break;
case 0x10 :
addressingtype = 128*1024;
break;
case 0x20 :
addressingtype = 256*1024;
break;
case 0x30 :
addressingtype = 512*1024;
break;
default:
addressingtype = 0;
}
// Check data bit width
bit2_3 = value & 0xc;
switch(bit2_3){
case 0 :
datawidth = 4;
break;
case 0x4 :
datawidth = 8;
break;
case 0x8 :
datawidth = 16;
break;
default:
datawidth = 0;
}
memfound = (addressingtype << datawidth); // in Kb
memfound = memfound >> 3; // in KB
totalmemKB += memfound;
i++;
if(i<=7){
value = 0;
pci_read_config_byte(pcidev,(0x80+i),&value);
}
}
return totalmemKB;
//return 1024*1024;
} }

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@ -0,0 +1,88 @@
/* Dump the first 64 longs for devfn 0, bus 0
* i.e. the north bridge.
*/
jmp dumpnorth_skip
.section ".rom.data"
dn_banner: .string "dump northbridge: \r\n"
dn_done: .string "Done.\r\n"
dn_before: .string "Before setting values: \r\n"
dn_after: .string "After setting values: \r\n"
#define NORTHBRIDGE_DEVFN 0xc000
#define NORTHBRIDGE1_DEVFN 0xc100
#define M1535_DEVFN 0x3800
#define M7101_DEVFN 0x8800
//#define M7101_DEVFN 0x3000
.previous
dumpnorth:
mov %esp, %ebp
CONSOLE_INFO_TX_STRING($dn_banner)
movl $NORTHBRIDGE_DEVFN, %ecx
// xorl %ecx, %ecx
1:
CONSOLE_INFO_TX_HEX32(%ecx)
CONSOLE_INFO_TX_CHAR($'-')
movl %ecx, %eax
PCI_READ_CONFIG_DWORD
CONSOLE_INFO_TX_HEX32(%eax)
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
addl $0x4, %ecx
cmpb $0, %cl
jne 1b
CONSOLE_INFO_TX_STRING($dn_done)
movl $NORTHBRIDGE1_DEVFN, %ecx
2:
CONSOLE_INFO_TX_HEX32(%ecx)
CONSOLE_INFO_TX_CHAR($'-')
movl %ecx, %eax
PCI_READ_CONFIG_DWORD
CONSOLE_INFO_TX_HEX32(%eax)
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
addl $0x4, %ecx
cmpb $0, %cl
jne 2b
CONSOLE_INFO_TX_STRING($dn_done)
movl $M1535_DEVFN, %ecx
3:
CONSOLE_INFO_TX_HEX32(%ecx)
CONSOLE_INFO_TX_CHAR($'-')
movl %ecx, %eax
PCI_READ_CONFIG_DWORD
CONSOLE_INFO_TX_HEX32(%eax)
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
addl $0x4, %ecx
cmpb $0, %cl
jne 3b
CONSOLE_INFO_TX_STRING($dn_done)
movl $M7101_DEVFN, %ecx
4:
CONSOLE_INFO_TX_HEX32(%ecx)
CONSOLE_INFO_TX_CHAR($'-')
movl %ecx, %eax
PCI_READ_CONFIG_DWORD
CONSOLE_INFO_TX_HEX32(%eax)
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
addl $0x4, %ecx
cmpb $0, %cl
jne 4b
CONSOLE_INFO_TX_STRING($dn_done)
mov %ebp, %esp
RETSP
dumpnorth_skip:

View file

@ -1,4 +1,4 @@
OBJS = jedec.o sst28sf040.o am29f040b.o mx29f002.c sst39sf020.o OBJS = jedec.o sst28sf040.o am29f040b.o mx29f002.c sst39sf020.o m29f400bt.o
CC = gcc -O2 -g CC = gcc -O2 -g
all: ${OBJS} all: ${OBJS}

View file

@ -32,6 +32,9 @@ struct flashchip {
#define WINBOND_ID 0xDA /* Winbond Manufacture ID code */ #define WINBOND_ID 0xDA /* Winbond Manufacture ID code */
#define W_29C020C 0x45 /* Winbond w29c020c device code*/ #define W_29C020C 0x45 /* Winbond w29c020c device code*/
#define ST_ID 0x20
#define ST_M29F400BT 0xD5
extern int probe_28sf040 (struct flashchip * flash); extern int probe_28sf040 (struct flashchip * flash);
extern int erase_28sf040 (struct flashchip * flash); extern int erase_28sf040 (struct flashchip * flash);
extern int write_28sf040 (struct flashchip * flash, char * buf); extern int write_28sf040 (struct flashchip * flash, char * buf);

View file

@ -35,6 +35,7 @@
#include "flash.h" #include "flash.h"
#include "jedec.h" #include "jedec.h"
#include "m29f400bt.h"
struct flashchip flashchips[] = { struct flashchip flashchips[] = {
{"Am29F040B", AMD_ID, AM_29F040B, NULL, 512, 64*1024, {"Am29F040B", AMD_ID, AM_29F040B, NULL, 512, 64*1024,
@ -51,6 +52,8 @@ struct flashchip flashchips[] = {
probe_39sf020, erase_39sf020, write_39sf020}, probe_39sf020, erase_39sf020, write_39sf020},
{"W29C020C", WINBOND_ID, W_29C020C, NULL, 256, 128, {"W29C020C", WINBOND_ID, W_29C020C, NULL, 256, 128,
probe_jedec, erase_jedec, write_jedec}, probe_jedec, erase_jedec, write_jedec},
{"M29F400BT", ST_ID, ST_M29F400BT , NULL, 512, 64*1024,
probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt},
{NULL,} {NULL,}
}; };