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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
fixed irq table with Dave Ashley's Patch
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parent
c36551cea1
commit
5f2d733946
1 changed files with 9 additions and 16 deletions
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@ -5,11 +5,12 @@
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#include <types.h>
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//static const unsigned char usbIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char usbIrqs[4] = { 11, 12, 10, 5 };
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static const unsigned char usbIrqs[4] = { 11, 10, 12, 5 };
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static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char slotIrqs[4] = { 10, 12, 5, 11 };
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static const unsigned char firewireIrqs[4] = { 12, 10, 5, 11 };
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static const unsigned char firewireIrqs[4] = {10, 12, 5, 11 };
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static const unsigned char vt8235Irqs[4] = { 5,10, 12, 11 }; // (DA) ???
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/*
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Our IDSEL mappings are as follows
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@ -32,11 +33,11 @@ static void pci_routing_fixup(void)
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* PINTD = IRQ5
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*/
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pci_write_config_byte(dev, 0x55, 0xb0);
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pci_write_config_byte(dev, 0x56, 0xac);
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pci_write_config_byte(dev, 0x56, 0xca);
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pci_write_config_byte(dev, 0x57, 0x50);
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}
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#if 1
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// firewire built into southbridge
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printk_info("setting firewire\n");
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pci_assign_irqs(0, 0x0d, firewireIrqs);
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@ -53,16 +54,9 @@ static void pci_routing_fixup(void)
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printk_info("setting pci slot\n");
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pci_assign_irqs(0, 0x14, slotIrqs);
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#endif
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printk_debug("4d0: 0x%02x\n", inb(0x4d0));
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printk_debug("4d1: 0x%02x\n", inb(0x4d1));
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#if 0
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outb(0, 0x4d0);
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outb(0, 0x4d1);
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#endif
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printk_debug("4d0: 0x%02x\n", inb(0x4d0));
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printk_debug("4d1: 0x%02x\n", inb(0x4d1));
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// vt8235 slot
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printk_info("setting pci slot\n");
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pci_assign_irqs(0, 0x11, vt8235Irqs);
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}
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@ -81,7 +75,6 @@ final_southbridge_fixup()
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printk_info("Southbridge fixup\n");
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nvram_on();
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// keyboard_on();
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pci_routing_fixup();
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}
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