elitegroup k7sem

src/mainboard/elitegroup/k7sem/Config

@@ -0,0 +1,23 @@
+arch i386
+mainboardinit cpu/i386/entry16.inc
+mainboardinit cpu/i386/entry32.inc
+ldscript cpu/i386/entry16.lds
+
+mainboardinit superio/sis/950/setup_serial.inc
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
+northsouthbridge sis/730
+# superio sis/950
+nsuperio sis/950 com1={1} floppy=1  lpt=1
+mainboardinit cpu/p6/earlymtrr.inc
+
+option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
+option FINAL_MAINBOARD_FIXUP=1
+option HAVE_PIRQ_TABLE=1
+option CONFIG_SIS_DISABLE_ETHERNET
+object mainboard.o
+object irq_tables.o
+keyboard pc80
+cpu p5
+cpu p6
+cpu k7

src/mainboard/elitegroup/k7sem/dll.inc

@@ -0,0 +1,7 @@
+/* Table for DLL Clock Control Register (0x8c - 0x8f), these
+   register values are very Mainboard specific */
+
+#	High Byte -> Register	Low Byte -> Value
+	.word	0x8c46
+	.word	0x8d70
+	.word	0x8e87

src/mainboard/elitegroup/k7sem/example.tftpboot.config

@@ -0,0 +1,36 @@
+# This will make a target directory of ./winfast
+# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE 
+# CONFIG TOOL. Make it absolute if you like
+target k7sem 
+
+# Elitegroup K7sem
+mainboard elitegroup/k7sem
+
+# Enable Serial Console for debugging
+# It will come up at 115200,8n1
+option SERIAL_CONSOLE=1
+
+# Enable MicroCode update and L2 Cache init for PII and PIII
+#option UPDATE_MICROCODE
+#option CONFIGURE_L2_CACHE
+
+# Use the internal VGA frame buffer device
+option HAVE_FRAMEBUFFER
+
+# Path to your kernel (vmlinux)
+# NOTE; you need a path to your test12 kernel here. 
+linux /usr/src/linux-2.2.17-beoboot-pyro1
+#linux /usr/src/linux-2.4.0-test12
+
+# Kernel command line parameters
+commandline root=/dev/nftla1
+
+# We're using disk on chip. Tell it where to find the docipl code
+docipl northsouthbridge/sis/730/ipl.S
+
+#option USE_DOC_MIL
+
+option STD_FLASH
+etherboot sis900
+
+

src/mainboard/elitegroup/k7sem/irq_tables.c

@@ -0,0 +1,27 @@
+#include <arch/pirq_routing.h>
+
+#define CHECKSUM 0x14
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,	/* u32 signature */
+	PIRQ_VERSION,	/* u16 version   */
+	32+16*4,	/* there can be total 5 devices on the bus */
+	0x00,		/* Bus 0 */
+	0x08,		/* Device 1, Function 0 */
+	0x0000,		/* reserve IRQ 11, 9, 5, for PCI */
+	0x1039,		/* Silicon Integrated System */
+	0x0008,		/* SiS 85C503/5513 ISA Bridge */
+	0x00,		/*  u8 miniport_data  - "crap" */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	CHECKSUM,	/*  u8 checksum       - mod 256 checksum must give zero */
+	{
+		/* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
+		{0x00, 0x08, {{0x41, 0xdcb8}, {0x42, 0xdcb8}, {0x43, 0xdcb8}, {0x44, 0xdcb8}},
+		 0x00, 0x00},
+		{0x00, 0x10, {{0x41, 0xdcb8}, {0x42, 0xdcb8}, {0x43, 0xdcb8}, {0x44, 0xdcb8}},
+		 0x00, 0x00},
+		{0x00, 0x48, {{0x41, 0xdcb8}, {0x42, 0xdcb8}, {0x43, 0xdcb8}, {0x44, 0xdcb8}},
+		 0x01, 0x00},
+		{0x00, 0x58, {{0x43, 0xdcb8}, {0x44, 0xdcb8}, {0x41, 0xdcb8}, {0x42, 0xdcb8}},
+		 0x02, 0x00},
+	}
+};

src/mainboard/elitegroup/k7sem/mainboard.c

@@ -0,0 +1,30 @@
+#include <printk.h>
+
+void
+mainboard_fixup(void)
+{
+}
+
+void
+final_mainboard_fixup(void)
+{
+	void fixk7msr_2dimms(unsigned long dimm1sizeK, 
+		unsigned long dimm2sizeK);
+	void final_southbridge_fixup(void);
+	void final_superio_fixup(void);
+	extern unsigned long slotsizeM[];
+	printk_info("elitegroup k7sem (and similar)...");
+
+	// we need to fix up the K7 MSRs. 
+	// to do this, we get the DIMM sizes in slot1 and 2, and 
+	// call fixk7msr_2dimms
+	// this is all very mainboard-specific ...
+
+	printk_err("Fixing mainboard for dimms %dK + %dK\n", 
+		slotsizeM[0], slotsizeM[1]);
+	fixk7msr_2dimms(slotsizeM[0], slotsizeM[1]);
+	final_southbridge_fixup();
+#ifndef USE_NEW_SUPERIO_INTERFACE
+	final_superio_fixup();
+#endif
+}