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UPSTREAM: mb/emulation/spike-riscv: Update UART address

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I updated my spike patch[1] to cleanly apply to current spike master.
As a side effect, the UART is now at 0x02100000.

[1]: https://github.com/riscv/riscv-isa-sim/pull/53

BUG=none
BRANCH=none
TEST=none

Change-Id: Ibc0fdb395099e54c8aec2d37b28c2c4489500b08
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 035cf71822
Original-Change-Id: I4cb09014619e230011486fa57636abe183baa4be
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/20126
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/531726
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2017-06-09 14:07:20 +02:00 • committed by chrome-bot
parent 4a015b8cf3
commit 5cae2c168d
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/emulation/spike-riscv/uart.c
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@ -20,5 +20,5 @@
uintptr_t uart_platform_base(int idx) uintptr_t uart_platform_base(int idx)
{ {
return (uintptr_t) 0x40001000; return (uintptr_t) 0x02100000;
} }