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UPSTREAM: cpu/amd/agesa: Unify init files

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The init files for the AMD families using the AGESA platform
initialization code are quite similar. So reduce the differences, by
using the same comments, variable names, console messages, and blank
lines.

BUG=none
BRANCH=none
TEST=none

Change-Id: I290453cd875ed445755de6218f9349bc9906e481
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 22f32c723c
Original-Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18507
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452891
This commit is contained in:
Paul Menzel 2017-02-27 01:26:42 +01:00 • committed by chrome-bot
parent 4fdc6148a9
commit 5b601e0fac
6 changed files with 10 additions and 13 deletions
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1
src/cpu/amd/agesa/family10/model_10_init.c
View file

@ -83,7 +83,6 @@ static void model_10_init(device_t dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);

1
src/cpu/amd/agesa/family12/model_12_init.c
View file

@ -88,7 +88,6 @@ static void model_12_init(device_t dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);

12
src/cpu/amd/agesa/family14/model_14_init.c
View file

@ -34,8 +34,9 @@
static void model_14_init(device_t dev)
{
u32 i;
u8 i;
msr_t msr;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
@ -58,11 +59,11 @@ static void model_14_init(device_t dev)
/* Set shadow WB, RdMEM, WrMEM */
msr.lo = msr.hi = 0;
wrmsr (0x259, msr);
msr.hi = msr.lo = 0x1e1e1e1e;
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
for (i = 0x268; i <= 0x26f; i++)
wrmsr(i, msr);
for (msrno = 0x268; msrno <= 0x26f; i++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
@ -97,6 +98,7 @@ static void model_14_init(device_t dev)
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
@ -108,8 +110,6 @@ static void model_14_init(device_t dev)
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
printk(BIOS_SPEW, "%s done.\n", __func__);
}
static struct device_operations cpu_dev_ops = {

2
src/cpu/amd/agesa/family15rl/model_15_init.c
View file

@ -130,7 +130,7 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */
{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */
{ 0, 0 },
};

4
src/cpu/amd/agesa/family15tn/model_15_init.c
View file

@ -129,8 +129,8 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */
{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */
{ X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */
{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */
{ 0, 0 },
};

3
src/cpu/amd/agesa/family16kb/model_16_init.c
View file

@ -78,7 +78,6 @@ static void model_16_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr);
}
/* Enable the local CPU APICs */
setup_lapic();
@ -114,7 +113,7 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */
{ X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */
{ 0, 0 },
};