mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
pu-dls for asus
This commit is contained in:
Ronald G. Minnich
parent
8955627c92
commit
5b2d475518
10 changed files with 1013 additions and 0 deletions
299
src/mainboard/asus/pu-dls/Config
Normal file
299
src/mainboard/asus/pu-dls/Config
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
arch i386
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit linuxBIOS entry code
|
||||
##
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
mainboardinit cpu/i386/entry32.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
ldscript cpu/i386/entry32.lds
|
||||
|
||||
##
|
||||
## Test for logical cpu thats not BSP
|
||||
## This is hyperthreading!
|
||||
## it may break!
|
||||
##
|
||||
#mainboardinit cpu/i786/logical_cpu.inc
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where linuxBIOS is entered)
|
||||
##
|
||||
mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE
|
||||
ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE
|
||||
|
||||
mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE
|
||||
ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Startup code for secondary CPUS
|
||||
##
|
||||
#mainboardinit arch/i386/smp/secondary.inc
|
||||
#mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
## This is the early phase of linuxBIOS startup
|
||||
## Things are delicate and we test to see if we should
|
||||
## failover to another image.
|
||||
|
||||
mainboardinit northbridge/intel/E7501/reset_test.inc
|
||||
mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE
|
||||
mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE
|
||||
ldscript mainboard/intel/Clearwater533/failover.lds USE_FALLBACK_IMAGE
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
|
||||
##
|
||||
## Setup our mtrrs
|
||||
##
|
||||
mainboardinit cpu/i786/earlymtrr.inc
|
||||
|
||||
##
|
||||
## TESTING!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
##
|
||||
mainboardinit mainboard/intel/Clearwater/preserial.inc
|
||||
|
||||
##
|
||||
## Setup the serial port
|
||||
##
|
||||
mainboardinit superio/winbond/w83627hf/setup_serial.inc
|
||||
#mainboardinit superio/winbond/w83627hf/setup_led.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
mainboardinit arch/i386/lib/console.inc
|
||||
|
||||
mainboardinit ram/ramtest.inc
|
||||
option RAMTEST=1
|
||||
|
||||
#Debug SMJ
|
||||
mainboardinit ram/dump_northbridge.inc
|
||||
#mainboardinit mainboard/intel/Clearwater/dumpdev.inc
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit southbridge/intel/82801ca/smbus.inc
|
||||
mainboardinit southbridge/intel/82801ca/smbus_read_block.inc
|
||||
mainboardinit southbridge/intel/82801ca/smbus_noop_read_block.inc
|
||||
mainboardinit southbridge/intel/82801ca/smbus_read_byte.inc
|
||||
|
||||
#debugging
|
||||
mainboardinit sdram/generic_dump_spd.inc USE_FALLBACK_IMAGE
|
||||
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
northbridge intel/E7501
|
||||
southbridge intel/82801ca
|
||||
southbridge intel/82870
|
||||
#nsuperio NSC/pc87309 com1={1} com2={1} floppy=1 lpt=1 keyboard=1
|
||||
nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1
|
||||
dir /src/pc80
|
||||
dir /src/superio/winbond/w83627hf
|
||||
dir /src/ram/
|
||||
cpu p5
|
||||
cpu p6
|
||||
cpu i786
|
||||
|
||||
##
|
||||
## We'll need a udelay function
|
||||
##
|
||||
|
||||
option CONFIG_UDELAY_TSC=1
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
object mainboard.o
|
||||
#object mtrr_values.o
|
||||
object mptable.o HAVE_MP_TABLE
|
||||
object irq_tables.o HAVE_PIRQ_TABLE
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Location of the DIMM EEPROMS on the SMBUS
|
||||
## This is fixed into a narrow range by the DIMM package standard.
|
||||
##
|
||||
option SMBUS_MEM_CHANNEL_OFF=4
|
||||
option SMBUS_MEM_DEVICE_START=(0xa << 3)
|
||||
option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +2)
|
||||
option SMBUS_MEM_DEVICE_INC=1
|
||||
|
||||
##
|
||||
## Customize our winbond superio chip for this motherboard
|
||||
##
|
||||
#option SIO_BASE=0x2e
|
||||
#option SIO_SYSTEM_CLK_INPUT=SIO_SYSTEM_CLK_INPUT_48MHZ
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
#option HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code for using cache as RAM
|
||||
##
|
||||
#option USE_CACHE_RAM=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
option HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
option HAVE_PIRQ_TABLE=1
|
||||
|
||||
|
||||
##
|
||||
## Do not build special code to the keyboard
|
||||
##
|
||||
option NO_KEYBOARD=1
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
option HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option tabe table
|
||||
##
|
||||
option HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
option SMP=1
|
||||
option MAX_CPUS=4
|
||||
option MAX_PHYSICAL_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
option IOAPIC=1
|
||||
|
||||
##
|
||||
## MEMORY_HOLE instructs earlymtrr.inc to
|
||||
## enable caching from 0-640KB and to disable
|
||||
## caching from 640KB-1MB using fixed MTRRs
|
||||
##
|
||||
## Enabling this option breaks SMP because secondary
|
||||
## CPU identification depends on only variable MTRRs
|
||||
## being enabled.
|
||||
##
|
||||
nooption MEMORY_HOLE
|
||||
|
||||
##
|
||||
## Don't do a generic MTRR setup
|
||||
## Instead use values from the fixed_mtrr_values array
|
||||
##
|
||||
#option HAVE_MTRR_TABLE=1
|
||||
|
||||
##
|
||||
## Enable both fixed and variable MTRRS
|
||||
## When we setup MTRRs in mtrr.c
|
||||
##
|
||||
## We must setup the fixed mtrrs or we confuse SMP secondary
|
||||
## processor identification
|
||||
##
|
||||
#option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
|
||||
|
||||
|
||||
##
|
||||
## Figure out which type of linuxBIOS image to build
|
||||
## If we aren't a fallback image we must be a normal image
|
||||
## This is useful for optional includes
|
||||
##
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
option ROM_SIZE=1048576
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
option ROM_IMAGE_SIZE=44288
|
||||
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
option _RAMBASE=0x00008000
|
||||
|
||||
## For the trick of using cache as ram
|
||||
## put the fake ram location at this address
|
||||
#option CACHE_RAM_BASE=0xfff70000
|
||||
#option CACHE_RAM_SIZE=0x00010000
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
option STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 8K heap
|
||||
##
|
||||
option HEAP_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
option MAINBOARD_PART_NUMBER=Tiger-i7501
|
||||
option MAINBOARD_VENDOR=Tyan
|
||||
|
||||
option PYRO_SERIAL=1
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Compute the location and size of where this firmware image
|
||||
## (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||
##
|
||||
expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE - 65536))
|
||||
expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE*0)
|
||||
|
||||
|
||||
##
|
||||
## Compute the start location and size size of
|
||||
## The linuxBIOS bootloader.
|
||||
##
|
||||
#expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
||||
#expr ZKERNEL_START = 0xfff00000 + (USE_NORMAL_IMAGE * 0x10000)
|
||||
expr ZKERNEL_START = 0xfff80000 + (USE_FALLBACK_IMAGE * 0x70000 )
|
||||
|
||||
|
||||
expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Compute where this copy of linuxBIOS will start in the boot rom
|
||||
##
|
||||
#expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE
|
||||
#expr _ROMBASE = 0xffff0000 - (USE_NORMAL_IMAGE*0x10000)
|
||||
expr _ROMBASE = 0x100000000 - (USE_NORMAL_IMAGE*0x10000) - ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Compute a range of ROM that can cached to speed of linuxBIOS,
|
||||
## execution speed.
|
||||
##
|
||||
expr XIP_ROM_SIZE = 65536
|
||||
expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
|
||||
27
src/mainboard/asus/pu-dls/STATUS
Normal file
27
src/mainboard/asus/pu-dls/STATUS
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# These are keyword-value pairs.
|
||||
# a : separates the keyword from the value
|
||||
# the value is arbitrary text delimited by newline.
|
||||
# continuation, if needed, will be via the \ at the end of a line
|
||||
# comments are indicated by a '#' as the first character.
|
||||
# the keywords are case-INSENSITIVE
|
||||
owner:
|
||||
email:
|
||||
#status: One of unsupported, unstable, stable
|
||||
status: unstable
|
||||
explanation: Brand new
|
||||
flash-types: SST 49LF004 FirmWare Hub. Intel 82802ac8 FWH (8Mbit) or 82802ab8 (4Mbit) can be substituted
|
||||
payload-types: etherboot, memtest86, pforth (an embedded Forth environment)
|
||||
# e.g. linux, plan 9, wince, etc.
|
||||
OS-types: linux
|
||||
# e.g. "Plan 9 interrupts don't work on this chipset"
|
||||
OS-issues:
|
||||
console-types: serial
|
||||
# vga is unsupported, unstable, or stable
|
||||
vga: unsupported
|
||||
# Last-known-good follows the internationl date standard: day/month/year
|
||||
last-known-good: 04/12/2003
|
||||
Comments:
|
||||
Links:
|
||||
Mainboard-revision: 1
|
||||
# What other mainboards are like this one? List them here.
|
||||
AKA:
|
||||
84
src/mainboard/asus/pu-dls/cmos.layout
Normal file
84
src/mainboard/asus/pu-dls/cmos.layout
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 2 hyper_threading
|
||||
396 1 e 1 thermal_monitoring
|
||||
400 1 e 1 power_on_after_fail
|
||||
401 1 e 1 ECC_memory
|
||||
#402 1 e 2 hda_disk
|
||||
#403 1 e 2 hdb_disk
|
||||
#404 1 e 2 hdc_disk
|
||||
#405 1 e 2 hdd_disk
|
||||
#406 2 e 7 boot_device
|
||||
408 4 e 9 CPU_clock_speed
|
||||
412 4 e 6 debug_level
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fall Back
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
#7 0 Network
|
||||
#7 1 HDD
|
||||
#7 2 Floppy
|
||||
#7 3 ROM
|
||||
9 15 800 MHZ
|
||||
9 11 900 MHZ
|
||||
9 13 1 GHZ
|
||||
9 9 1.1 GHZ
|
||||
9 14 1.2 GHZ
|
||||
9 10 1.3 GHZ
|
||||
9 12 1.4 GHZ
|
||||
9 8 1.5 GHZ
|
||||
9 7 1.6 GHZ
|
||||
9 3 1.7 GHZ
|
||||
9 5 1.8 GHZ
|
||||
9 1 1.9 GHZ
|
||||
9 6 2.0 GHZ
|
||||
9 2 2.1 GHZ
|
||||
9 4 2.2 GHZ
|
||||
9 0 2.3 GHZ
|
||||
|
||||
40
src/mainboard/asus/pu-dls/defines
Normal file
40
src/mainboard/asus/pu-dls/defines
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
#define S0_WAIT() \
|
||||
movw $0x3fd, %dx ;\
|
||||
9: inb %dx, %al ;\
|
||||
test $0x40, %al ;\
|
||||
je 9b
|
||||
|
||||
#define S0_EMIT(char) \
|
||||
9: movw $0x3fd, %dx ;\
|
||||
inb %dx, %al ;\
|
||||
test $0x20, %al ;\
|
||||
je 9b ;\
|
||||
movb $char,%al ;\
|
||||
movw $0x3f8, %dx ;\
|
||||
outb %al, %dx
|
||||
|
||||
#define __CONSOLE_INLINE_TX_HEX8(byte) \
|
||||
movb byte, %al ; \
|
||||
shr $4, %al ; \
|
||||
add $'0', %al ; \
|
||||
cmp $'9', %al ; \
|
||||
jle 9f ; \
|
||||
add $39, %al ; \
|
||||
9: ; \
|
||||
movw $0x3f8, %dx ;\
|
||||
outb %al, %dx ;\
|
||||
10: movw $0x3fd, %dx ;\
|
||||
inb %dx, %al ;\
|
||||
test $0x20, %al ;\
|
||||
je 10b ;\
|
||||
movw $0x3f8, %dx ;\
|
||||
mov byte, %al ; \
|
||||
and $0x0f, %al ; \
|
||||
add $'0', %al ; \
|
||||
cmp $'9', %al ; \
|
||||
jle 9f ; \
|
||||
add $39, %al ; \
|
||||
9: ; \
|
||||
movw $0x3f8, %dx ;\
|
||||
outb %al, %dx
|
||||
|
||||
30
src/mainboard/asus/pu-dls/example-fallback.config
Normal file
30
src/mainboard/asus/pu-dls/example-fallback.config
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
target tiger_i7501-fallback
|
||||
|
||||
# Intel Clearwater (cw2) mainboard
|
||||
mainboard tyan/tiger-i7501
|
||||
|
||||
# Enable Serial Console for debugging
|
||||
# It will come up at 115200,8n1
|
||||
option SERIAL_CONSOLE=1
|
||||
|
||||
# Enable MicroCode update and L2 Cache init for PII and PIII
|
||||
option UPDATE_MICROCODE=1
|
||||
#option CONFIGURE_L2_CACHE=1
|
||||
|
||||
# Use the internal VGA frame buffer device
|
||||
#option HAVE_FRAMEBUFFER=1
|
||||
|
||||
option USE_ELF_BOOT=1
|
||||
|
||||
option USE_GENERIC_ROM=1
|
||||
|
||||
option STD_FLASH=1
|
||||
|
||||
option USE_FALLBACK_IMAGE = 1
|
||||
|
||||
option HAVE_PIRQ_TABLE=1
|
||||
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
|
||||
#payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf
|
||||
|
||||
30
src/mainboard/asus/pu-dls/example-normal.config
Normal file
30
src/mainboard/asus/pu-dls/example-normal.config
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
target tiger_i7501-primary
|
||||
|
||||
# Intel Clearwater (cw2) mainboard
|
||||
mainboard tyan/tiger-i7501
|
||||
|
||||
# Enable Serial Console for debugging
|
||||
# It will come up at 115200,8n1
|
||||
option SERIAL_CONSOLE=1
|
||||
|
||||
# Enable MicroCode update and L2 Cache init for PII and PIII
|
||||
option UPDATE_MICROCODE=1
|
||||
#option CONFIGURE_L2_CACHE=1
|
||||
|
||||
# Use the internal VGA frame buffer device
|
||||
#option HAVE_FRAMEBUFFER=1
|
||||
|
||||
option USE_ELF_BOOT=1
|
||||
|
||||
option USE_GENERIC_ROM=1
|
||||
|
||||
option STD_FLASH=1
|
||||
|
||||
option USE_FALLBACK_IMAGE = 0
|
||||
|
||||
option HAVE_PIRQ_TABLE=1
|
||||
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
|
||||
#payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf
|
||||
|
||||
41
src/mainboard/asus/pu-dls/irq_tables.c
Normal file
41
src/mainboard/asus/pu-dls/irq_tables.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*17, /* there can be total 17 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0xf8, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0, /* Vendor */
|
||||
0, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xd3, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{0,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0x10, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x1,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x2,0x8, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x2, 0},
|
||||
{0x2,0x10, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x3, 0},
|
||||
{0x1,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x3,0x8, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x1, 0},
|
||||
{0,0xe8, {{0x60, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xe9, {{0, 0xdef8}, {0x63, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xf0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x8, {{0x61, 0xdcb8}, {0x62, 0xdcb8}, {0x61, 0xdcb8}, {0x62, 0xdcb8}}, 0x4, 0},
|
||||
{0x4,0x10, {{0x63, 0xdcb8}, {0x60, 0xdcb8}, {0x63, 0xdcb8}, {0x60, 0xdcb8}}, 0x5, 0},
|
||||
{0x4,0x18, {{0x69, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x20, {{0x68, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x28, {{0x6b, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x30, {{0x6a, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xfb, {{0, 0xdef8}, {0x61, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
}
|
||||
};
|
||||
255
src/mainboard/asus/pu-dls/mainboard.c
Normal file
255
src/mainboard/asus/pu-dls/mainboard.c
Normal file
|
|
@ -0,0 +1,255 @@
|
|||
#include <arch/io.h>
|
||||
#include <part/mainboard.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <southbridge/intel/82801.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <pc80/isa_dma.h>
|
||||
#include <cpu/i786/multiplier.h>
|
||||
#include <cpu/i786/thermal_monitoring.h>
|
||||
#include <cpu/p6/msr.h>
|
||||
// #include <superio/w83627hf.h>
|
||||
#include <superio/generic.h>
|
||||
#include <subr.h>
|
||||
#include <smbus.h>
|
||||
#include <ramtest.h>
|
||||
// #include <northbridge/intel/82860/rdram.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
|
||||
#define SMBUS_MEM_DEVICE_0 (0xa << 3)
|
||||
extern int rdram_chips; /* number of ram chips on the rimms */
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0, 6, 1, 7
|
||||
};
|
||||
|
||||
#ifndef CPU_CLOCK_MULTIPLIER
|
||||
#define CPU_CLOCK_MULTIPLIER XEON_X17
|
||||
#endif
|
||||
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
#define MAINBOARD_POWER_OFF 2
|
||||
|
||||
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
void dump_pci_dev(int bus, int dev, int fn)
|
||||
{
|
||||
|
||||
unsigned int offset = 0x80000000;
|
||||
unsigned int i;
|
||||
unsigned short devfn;
|
||||
unsigned char byte;
|
||||
|
||||
devfn = (dev <<3) | fn;
|
||||
offset |= (bus << 16) | (devfn << 8);
|
||||
|
||||
printk_notice("dump %u:%u.%u:\n", bus,dev,fn);
|
||||
|
||||
for(i=0; i<256; i++) {
|
||||
|
||||
if(! (i & 0x0f))
|
||||
printk_notice( "\n%02x: ", i);
|
||||
|
||||
pcibios_read_config_byte(bus, devfn, i, &byte);
|
||||
printk_notice( "%02x ", byte);
|
||||
}
|
||||
|
||||
printk_notice("\nDone.\n\n");
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static void set_power_on_after_power_fail(int setting)
|
||||
{
|
||||
switch(setting) {
|
||||
case MAINBOARD_POWER_ON:
|
||||
default:
|
||||
ich3_power_after_power_fail(1);
|
||||
// w832627hf_power_after_power_fail(POWER_ON);
|
||||
break;
|
||||
case MAINBOARD_POWER_OFF:
|
||||
ich3_power_after_power_fail(0);
|
||||
// w832627hf_power_after_power_fail(POWER_OFF);
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void set_thermal_monitoring(int thermal_monitoring)
|
||||
{
|
||||
int tm_high,tm_low;
|
||||
|
||||
rdmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
if(thermal_monitoring != THERMAL_MONITORING_OFF) {
|
||||
tm_low |= THERMAL_MONITORING_SET;
|
||||
}
|
||||
else {
|
||||
tm_low &= ~THERMAL_MONITORING_SET;
|
||||
}
|
||||
wrmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
return;
|
||||
}
|
||||
|
||||
void mainboard_fixup(void)
|
||||
{
|
||||
int cpu_clock_multiplier;
|
||||
int power_on_after_power_fail;
|
||||
int thermal_monitoring;
|
||||
|
||||
printk_notice("CW2 mainboard fixup:\n");
|
||||
ich3_enable_ioapic();
|
||||
p64h2_enable_ioapic();
|
||||
ich3_enable_serial_irqs();
|
||||
ich3_enable_ide(1,1);
|
||||
// test, SMJ
|
||||
// ich3_rtc_init();
|
||||
ich3_lpc_route_dma(0xff);
|
||||
isa_dma_init();
|
||||
ich3_1e0_misc();
|
||||
ich3_1f0_misc();
|
||||
|
||||
// SMJ dump some registers!
|
||||
#if 0
|
||||
dump_pci_dev(0, 0, 0);
|
||||
|
||||
printk_notice("1st bridge:\n");
|
||||
dump_pci_dev(0, 3, 0);
|
||||
|
||||
|
||||
printk_notice("APIC:\n");
|
||||
dump_pci_dev(1, 0x1c, 0);
|
||||
dump_pci_dev(1, 0x1e, 0);
|
||||
|
||||
printk_notice("bridge:\n");
|
||||
dump_pci_dev(1, 0x1d, 0);
|
||||
dump_pci_dev(1, 0x1f, 0);
|
||||
|
||||
printk_notice("ether (connected to 1:0x1f.0):\n");
|
||||
dump_pci_dev(3, 0x7, 0);
|
||||
dump_pci_dev(3, 0x7, 1);
|
||||
#endif
|
||||
|
||||
// test only SMJ
|
||||
return;
|
||||
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
if(get_option(&cpu_clock_multiplier, "CPU_clock_speed"))
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
ich3_set_cpu_multiplier(cpu_clock_multiplier);
|
||||
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
if(get_option(&power_on_after_power_fail, "power_on_after_power_fail"))
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
set_power_on_after_power_fail(power_on_after_power_fail);
|
||||
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
if(get_option(&thermal_monitoring, "thermal_monitoring"))
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
set_thermal_monitoring(thermal_monitoring);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
ich3_hard_reset();
|
||||
}
|
||||
|
||||
#ifdef USE_CACHE_RAM
|
||||
|
||||
void cache_ram_start(void)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = 0;
|
||||
/* displayinit MUST PRECEDE ALL PRINTK! */
|
||||
|
||||
#if 1
|
||||
displayinit();
|
||||
#endif
|
||||
printk_info("Finding PCI configuration type.\n");
|
||||
pci_set_method();
|
||||
printk_info("Setting up smbus controller\n");
|
||||
smbus_setup();
|
||||
ich3_rtc_init();
|
||||
printk_info("Selecting rdram i2c bus\n");
|
||||
// select_rdram_i2c();
|
||||
|
||||
#if 0
|
||||
display_smbus_spd();
|
||||
#endif
|
||||
|
||||
init_memory();
|
||||
|
||||
#if 0
|
||||
{
|
||||
unsigned long addr;
|
||||
for(addr = 0; addr < 0x20000000; addr += 0x02000000) {
|
||||
ram_fill(addr, addr + 0x400);
|
||||
}
|
||||
/* Do some dummy writes to flush a write cache, in the
|
||||
* processor.
|
||||
*/
|
||||
ram_fill(0xc0000000, 0xc0000400);
|
||||
for(addr = 0; addr < 0x20000000; addr += 0x02000000) {
|
||||
ram_verify(addr, addr + 0x400, 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if 1
|
||||
printk_debug("starting ramcheck\n");
|
||||
error |= ramcheck(0x00000000, 0x00080000, 40);
|
||||
error |= ramcheck(0x02000000, 0x02080000, 40);
|
||||
error |= ramcheck(0x04000000, 0x04080000, 40);
|
||||
error |= ramcheck(0x06000000, 0x06080000, 40);
|
||||
error |= ramcheck(0x08000000, 0x08080000, 40);
|
||||
error |= ramcheck(0x0a000000, 0x0a080000, 40);
|
||||
error |= ramcheck(0x0c000000, 0x0c080000, 40);
|
||||
error |= ramcheck(0x0e000000, 0x0e080000, 40);
|
||||
error |= ramcheck(0x1a000000, 0x1a080000, 40);
|
||||
#if 0
|
||||
error |= ramcheck(0x10000000, 0x10080000, 20);
|
||||
error |= ramcheck(0x12000000, 0x12080000, 20);
|
||||
error |= ramcheck(0x14000000, 0x14080000, 20);
|
||||
error |= ramcheck(0x16000000, 0x16080000, 20);
|
||||
error |= ramcheck(0x18000000, 0x18080000, 20);
|
||||
error |= ramcheck(0x1a000000, 0x1a080000, 20);
|
||||
error |= ramcheck(0x1c000000, 0x1c080000, 20);
|
||||
error |= ramcheck(0x1e000000, 0x1e080000, 20);
|
||||
#endif
|
||||
#endif
|
||||
#if 0
|
||||
error |= ramcheck(0x00000000, 0x00080000, 20);
|
||||
#endif
|
||||
#if 0
|
||||
display_rdram_regs(rdram_chips );
|
||||
#endif
|
||||
#if 0
|
||||
display_mch_regs();
|
||||
#endif
|
||||
if (error) {
|
||||
printk_err("Something isn't working!!!\n");
|
||||
while(1);
|
||||
} else {
|
||||
printk_info("Leaving cacheram...\n");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
158
src/mainboard/asus/pu-dls/mptable.c
Normal file
158
src/mainboard/asus/pu-dls/mptable.c
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
/* generatred by MPTable, version 2.0.15*/
|
||||
/* as modified by RGM for LinuxBIOS */
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <string.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "LnxLabs ";
|
||||
static const char productid[12] = "Tyan i7500 ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "PCI ");
|
||||
smp_write_bus(mc, 4, "PCI ");
|
||||
smp_write_bus(mc, 5, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 4, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 5, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 8, 0x20, base);
|
||||
}
|
||||
}
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xa, 0x2, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xf, 0x2, 0xf);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x2, 0x12);
|
||||
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x11, 0x2, 0x11);
|
||||
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x7d, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x8, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x2, 0x11);
|
||||
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x2, 0x14);
|
||||
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x3, 0x0);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x3, 0x0); // slot 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x3, 0x4); // slot 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, 0x2, 0x13); // slot 3
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0xc, 0x2, 0x12); // slot 4
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0x4, 0x0);
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
|
||||
|
||||
/*
|
||||
MP Config Extended Table Entries:
|
||||
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: I/O address
|
||||
address base: 0xb000
|
||||
address range: 0x4000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: I/O address
|
||||
address base: 0x0
|
||||
address range: 0x100
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xa0000
|
||||
address range: 0x20000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xfc700000
|
||||
address range: 0x2500000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: prefetch address
|
||||
address base: 0xff600000
|
||||
address range: 0x500000
|
||||
--
|
||||
Bus Heirarchy
|
||||
bus ID: 5 bus info: 0x01 parent bus ID: 0--
|
||||
Compatibility Bus Address
|
||||
bus ID: 0 address modifier: add
|
||||
predefined range: 0x00000000--
|
||||
Compatibility Bus Address
|
||||
bus ID: 0 address modifier: add
|
||||
predefined range: 0x00000001 There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p
|
||||
",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
49
src/mainboard/asus/pu-dls/mtrr_values.c
Normal file
49
src/mainboard/asus/pu-dls/mtrr_values.c
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
#include <cpu/p6/mtrr.h>
|
||||
|
||||
/* We want to cache memory as efficiently as possible.
|
||||
*/
|
||||
#define RAM MTRR_TYPE_WRBACK
|
||||
/* We can't use Write Combining on a legacy frame buffer because
|
||||
* it is incompatible with EGA 16 color video modes...
|
||||
*/
|
||||
#define FB MTRR_TYPE_UNCACHABLE
|
||||
/* For areas that are supposed to cover roms it makes no
|
||||
* sense to cache writes.
|
||||
*/
|
||||
#define ROM MTRR_TYPE_WRPROT
|
||||
|
||||
|
||||
unsigned char fixed_mtrr_values[][4] = {
|
||||
/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */
|
||||
{FB, FB, FB, FB}, {FB, FB, FB, FB},
|
||||
|
||||
/* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue