mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
from dave ashley.
ron
This commit is contained in:
Ronald G. Minnich
parent
1103ba3c2a
commit
5aad3ba0d0
5 changed files with 210 additions and 36 deletions
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@ -190,9 +190,18 @@ biosint(
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eax = 64 * 1024;
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ret = 0;
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break;
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#ifdef CONFIG_INT21HANDLER
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case 0x15:
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ret=handleint21( &edi, &esi, &ebp, &esp,
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&ebx, &edx, &ecx, &eax, &flags);
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break;
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#endif
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default:
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printk_info(__FUNCTION__ ": Unsupport int #0x%x\n",
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intnumber);
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#ifdef CONFIG_UNSUPPORTINT_RECOVER
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unsupportint_recover();
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#endif
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break;
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}
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if (ret)
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@ -159,6 +159,13 @@ __asm__ (
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" ret\n"
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);
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#ifdef CONFIG_UNSUPPORTINT_RECOVER
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void unsupportint_recover(void)
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{
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__asm__ __volatile__ ( " jmp vgarestart \n" );
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}
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#endif
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void
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do_vgabios(void)
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{
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@ -192,6 +199,9 @@ do_vgabios(void)
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if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
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memcpy((void *) 0xc0000, buf, size);
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#ifdef VGABIOS_WRITE_PROTECT
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write_protect_vgabios();
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#endif
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for(i = 0; i < 16; i++)
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printk_debug("0x%x ", buf[i]);
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@ -44,4 +44,6 @@ cpu p6
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option MAINBOARD_PART_NUMBER=EPIA-M
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option MAINBOARD_VENDOR=VIA
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option CONFIG_INT21HANDLER=1
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option VGABIOS_WRITE_PROTECT=1
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option CONFIG_UNSUPPORTINT_RECOVER=1
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@ -10,7 +10,7 @@ static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char slotIrqs[4] = { 10, 12, 5, 11 };
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static const unsigned char firewireIrqs[4] = {10, 12, 5, 11 };
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static const unsigned char vt8235Irqs[4] = { 5,10, 12, 11 };
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static const unsigned char vgaIrqs[4] = { 11, 5, 12, 10 };
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/*
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Our IDSEL mappings are as follows
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@ -28,8 +28,8 @@ static void pci_routing_fixup(void)
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* on the PCB routing of PINTA-D
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*
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* PINTA = IRQ11
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* PINTB = IRQ12
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* PINTC = IRQ10
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* PINTB = IRQ10
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* PINTC = IRQ12
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* PINTD = IRQ5
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*/
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pci_write_config_byte(dev, 0x55, 0xb0);
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@ -46,10 +46,18 @@ static void pci_routing_fixup(void)
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printk_info("setting usb\n");
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pci_assign_irqs(0, 0x10, usbIrqs);
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// VT8235 + sound hardware
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printk_info("setting vt8235\n");
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pci_assign_irqs(0, 0x11, vt8235Irqs);
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// Ethernet built into southbridge
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printk_info("setting ethernet\n");
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pci_assign_irqs(0, 0x12, enetIrqs);
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// VGA
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printk_info("setting vga\n");
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pci_assign_irqs(1, 0x00, vgaIrqs);
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// PCI slot
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printk_info("setting pci slot\n");
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pci_assign_irqs(0, 0x14, slotIrqs);
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@ -59,10 +67,27 @@ static void pci_routing_fixup(void)
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pci_assign_irqs(0, 0x11, vt8235Irqs);
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}
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static unsigned char vt1211hwmonitorinits[]={
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0x10,0x3, 0x11,0x10, 0x12,0xd, 0x13,0x7f,
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0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a,
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0x18,0x0, 0x19,0x0, 0x1a,0x0, 0x1b,0x0,
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0x1d,0xff, 0x1e,0x0, 0x1f,0x73, 0x20,0x67,
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0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2,
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0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x0,
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0x2a,0x0, 0x2b,0xff, 0x2c,0x0, 0x2d,0xff,
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0x2e,0x0, 0x2f,0xff, 0x30,0x0, 0x31,0xff,
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0x32,0x0, 0x33,0xff, 0x34,0x0, 0x39,0xff,
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0x3a,0x0, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
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0x3e,0x0, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
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0x46,0xff, 0x47,0x50, 0x4a,0x3, 0x4b,0xc0,
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0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77,
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0x5c,0x0, 0x5f,0x33, 0x40,0x1};
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void
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mainboard_fixup()
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{
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struct pci_dev *dev;
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int i;
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printk_info("Mainboard fixup\n");
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northbridge_fixup();
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@ -74,8 +99,64 @@ final_southbridge_fixup()
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{
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printk_info("Southbridge fixup\n");
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nvram_on();
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pci_routing_fixup();
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// nvram_on();
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// pci_routing_fixup();
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northbridge_fixup();
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southbridge_fixup();
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dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
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if(dev) {
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// enable shadow RAM for c0000-cffff
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pci_write_config_byte(dev, 0x61, 0xff);
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// enable 2x + 4x agp
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pci_write_config_byte(dev, 0xac, 0x2f);
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pci_write_config_byte(dev, 0xae, 0x04);
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}
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// Activate the vt1211 hardware monitor
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outb(0x87,0x2e); // enter config mode part a
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outb(0x87,0x2e); // enter config mode part b
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outb(7,0x2e); // device index#
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outb(0x0b,0x2f); // select hardware monitor LDN
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outb(0x30,0x2e); // activate index#
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outb(1,0x2f);
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outb(0xaa,0x2e); // exit config mode
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// initialize vt1211 hardware monitor registers, which are at 0xECXX
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for(i=0;i<sizeof(vt1211hwmonitorinits);i+=2)
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outb(vt1211hwmonitorinits[i+1],0xec00+vt1211hwmonitorinits[i]);
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// clear out cmos contents, it seems to cause trouble
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for(i=14;i<256;++i)
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{
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outb(i,0x74);
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outb(0,0x75);
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}
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#ifdef CONFIG_EPIAMVERSIONSTRING
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// Use CMOS bytes 128+ to store version string
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for(i=0;;++i)
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{
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char c;
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outb(i+128,0x74);
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c=CONFIG_EPIAMVERSIONSTRING[i];
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outb(c,0x75);
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if(!c) break;
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}
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#endif
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}
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void write_protect_vgabios(void)
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{
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struct pci_dev *dev;
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printk_info("write_protect_vgabios\n");
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dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
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if(dev)
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pci_write_config_byte(dev, 0x61, 0xaa);
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}
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void
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@ -85,3 +166,33 @@ final_mainboard_fixup()
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final_southbridge_fixup();
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}
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int handleint21( unsigned long *edi, unsigned long *esi, unsigned long *ebp,
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unsigned long *esp, unsigned long *ebx, unsigned long *edx,
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unsigned long *ecx, unsigned long *eax, unsigned long *flags)
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{
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int res=-1;
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switch(*eax&0xffff)
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{
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case 0x5f19:
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break;
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case 0x5f18:
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*eax=0x5f;
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*ebx=0x15; // MCLK = 133, 32M frame buffer
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res=0;
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break;
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case 0x5f02:
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*eax=0x5f;
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*ebx=0 | (3<<8);
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*ecx=5 | (0<<8) | (0<<16);
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res=0;
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break;
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case 0x5f0f:
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*eax=0x5f;
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*ebx=0;
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*ecx=0;
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*edx=0;
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res=0;
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break;
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}
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return res;
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}
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@ -37,10 +37,23 @@ raminit:
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CS_WRITE($0x55, $0x07)
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/* DRAM MA Map Type */
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CS_WRITE($0x58, $0xc0)
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/* CS_WRITE($0x58, $0xc0)*/
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//#define GETCHIP
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#undef GETCHIP
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#ifndef GETCHIP
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CS_WRITE($0x58, $0x71) // was 60 was 0x71 (DA) 20030722
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#else
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CS_WRITE($0x58, $0x40) // For GET memory
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#endif
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/* DRAM bank 0 - 3 size = 512M */
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#ifndef GETCHIP
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CS_WRITE($0x5a, $0x08)
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#else
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CS_WRITE($0x5a, $0x04) // For GET memory
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#endif
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CS_WRITE($0x5b, $0x08)
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CS_WRITE($0x5c, $0x08)
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CS_WRITE($0x5d, $0x08)
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@ -54,11 +67,19 @@ raminit:
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/* DRAM Arbitration Timer */
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CS_WRITE($0x65, $0x32)
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CS_WRITE($0x66, $0x01)
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CS_WRITE($0x68, $0x41)
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#ifndef GETCHIP
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CS_WRITE($0x68, $0x59) // was 0xf0 was 0x59 (DA) 20030722
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#else
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CS_WRITE($0x68, $0x55) // GET
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#endif
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/* DRAM Frequency */
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CS_WRITE($0x54, $0xe0)
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CS_WRITE($0x69, $0x25)
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#ifndef GETCHIP
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CS_WRITE($0x69, $0x2d)
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#else
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CS_WRITE($0x69, $0x25) // GET
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#endif
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/* Enable CKE */
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CS_WRITE($0x6b, $0x10)
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@ -67,61 +88,82 @@ raminit:
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CS_WRITE($0x6a, $0x00)
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/* Set heavy drive */
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#ifndef GETCHIP
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CS_WRITE($0x6d, $0x44)
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#else
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CS_WRITE($0x6d, $0x55) // GET
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CS_WRITE($0x6c, $0x84) // GET
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#endif
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xorl %esi,%esi
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ritop:
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/* NOP Command Enable */
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CS_WRITE($0x6b, $0x01)
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/* read a double word from any address of the dimm */
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movl %ds:(%esi), %eax
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movl 0x1f000(%esi), %eax
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DELAY(loop200)
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/* All bank Precharge Command Enable */
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CS_WRITE($0x6b, $0x02)
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movl %ds:(%esi), %eax
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movl 0x1f100(%esi), %eax
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/* MSR Enable */
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CS_WRITE($0x6b, $0x03)
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/* read 0x2000h */
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movl $0x2000, %esi
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movl %ds:(%esi), %eax
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movl 0x2000(%esi), %eax
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// movl $0x2000,%esi
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// movl (%esi), %eax
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// movl $0x4002000, %ecx
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// movl (%esi), %eax
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/* read 0x800h */
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movl $0x800, %esi
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movl %ds:(%esi), %eax
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movl 0x800(%esi), %eax
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// movl $0x800,%esi
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// movl (%esi), %eax
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// movl $0x4000800, %esi
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// movl (%esi), %eax
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/* All banks Precharge Command Enable */
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CS_WRITE($0x6b, $0x02)
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movl %ds:(%esi), %eax
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movl 0x1f200(%esi), %eax
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/* CBR Cycle Enable */
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CS_WRITE($0x6b, $0x04)
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/* Read 8 times */
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movl %ds:(%esi), %eax
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movl 0x1f300(%esi), %eax
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DELAY(loop100)
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movl %ds:(%esi), %eax
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movl 0x1f400(%esi), %eax
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DELAY(loop100)
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movl %ds:(%esi), %eax
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movl 0x1f500(%esi), %eax
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DELAY(loop100)
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movl %ds:(%esi), %eax
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movl 0x1f600(%esi), %eax
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DELAY(loop100)
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movl %ds:(%esi), %eax
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movl 0x1f700(%esi), %eax
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DELAY(loop100)
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movl %ds:(%esi), %eax
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movl 0x1f800(%esi), %eax
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DELAY(loop100)
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movl %ds:(%esi), %eax
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movl 0x1f900(%esi), %eax
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DELAY(loop100)
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movl %ds:(%esi), %eax
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movl 0x1fa00(%esi), %eax
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DELAY(loop100)
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/* MSR Enable */
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CS_WRITE($0x6b, $0x03)
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/* 0x150 if CAS Latency 2 or 0x350 CAS Latency 2.5 */
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movl $0x350, %esi
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movl %ds:(%esi), %eax
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movl 0x350(%esi), %ecx
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// movl (%ecx), %eax
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// movl $0x4000350, %ecx
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// movl (%ecx), %eax
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/* Normal SDRAM Mode */
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CS_WRITE($0x6b, $0x58)
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#ifdef GETCHIP
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addl $0x40*0x100000,%esi
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cmpl $0x80*0x100000,%esi
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jne ritop
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#endif
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/* Set the refreash rate */
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CS_WRITE($0x6a, $0x43)
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CS_WRITE($0x67, $0x22)
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