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UPSTREAM: mb/gigabyte/ga-g41m-es2l: Add timestamps in romstage

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BUG=none
BRANCH=none
TEST=none

Change-Id: I9b89a0b86082e5b57a53c5c7c6fd9fe0c9db6167
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1222162d12
Original-Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/510762
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-05-01 18:33:39 +02:00 • committed by chrome-bot
parent 8c588258d7
commit 5a693df048
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
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@ -31,6 +31,7 @@
#include <arch/stages.h>
#include <cbmem.h>
#include <northbridge/intel/x4x/iomap.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
@ -135,6 +136,9 @@ void mainboard_romstage_entry(unsigned long bist)
u8 boot_path = 0;
u8 s3_resume;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
/* Disable watchdog timer */
RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
@ -160,7 +164,9 @@ void mainboard_romstage_entry(unsigned long bist)
boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");