From 5917206641611fb593b9b7064dbadf4ea859d66f Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Wed, 6 Feb 2008 02:36:50 +0000 Subject: [PATCH] Cache the ROM to speed up stage2 and payload decompression. Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below. Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1. Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload(). "The problem is a transaction depth issue and bottlenecks inside the GX and LX that go across PCI. The conditions are very complicated but it comes down to we need write serialization for writes to PCI. If you look in the data book you can't have write serialization and the cache enabled on a given area. During coreboot we don't have to worry about a write or a PCI bus master so I think we can enable caching the ROM. After coreboot we can't be sure what will happen in the system so we need to set it up to be safe. For example flashrom just clears the write protect bit. If the cache were enabled (no write serialization) and flashrom was writing the ROM we would be in a precarious position. A PCI bus master doing a read or a write that has a hit on a tag would cause enough bottleneck conditions that it might hit the bug. We could change flashrom but that doesn't help other tools. We need to leave the system in a safe state. Also, caching the ROM after it is no longer used doesn't make much sense. So, we need a call just before the payload runs to clean up the system." Signed-off-by: Marc Jones Acked-by: Carl-Daniel Hailfinger Acked-by: Ronald G. Minnich git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- arch/x86/Makefile | 2 +- arch/x86/ldscript.ld | 2 +- arch/x86/stage1.c | 9 ++++++--- include/arch/x86/amd_geodelx.h | 1 + mainboard/adl/msm800sev/stage1.c | 6 ++++++ mainboard/amd/norwich/stage1.c | 6 ++++++ mainboard/artecgroup/dbe61/stage1.c | 6 ++++++ mainboard/emulation/qemu-x86/stage1.c | 5 +++++ mainboard/pcengines/alix1c/stage1.c | 6 ++++++ northbridge/amd/geodelx/geodelxinit.c | 15 ++++++++++++++- util/lar/lar.h | 2 +- 11 files changed, 53 insertions(+), 7 deletions(-) diff --git a/arch/x86/Makefile b/arch/x86/Makefile index bff4210f49..487a8c3de2 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -157,7 +157,7 @@ $(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ) $(Q)$(OBJCOPY) --prefix-symbols=stage0_ $(obj)/stage0.o $(obj)/stage0-prefixed.o $(Q)printf " TEST $(subst $(shell pwd)/,,$(@))\n" - $(Q)test `wc -c < $(obj)/stage0.init` -gt 16128 && \ + $(Q)test `wc -c < $(obj)/stage0.init` -gt 20224 && \ printf "Error. Bootblock got too big.\n" || true $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" $(Q)$(NM) $(obj)/stage0.o | sort -u > $(obj)/stage0.init.map diff --git a/arch/x86/ldscript.ld b/arch/x86/ldscript.ld index 3d7a5c88fc..36e81292bd 100644 --- a/arch/x86/ldscript.ld +++ b/arch/x86/ldscript.ld @@ -28,7 +28,7 @@ ENTRY(_start) TARGET(binary) SECTIONS { - . = 0xffffc000 + 256; /* leave space for vpd */ + . = 0xffffb000 + 256; /* leave space for vpd */ .stage0_1 . : { _stage0_1 = .; diff --git a/arch/x86/stage1.c b/arch/x86/stage1.c index d8ef3e1d69..b768227152 100644 --- a/arch/x86/stage1.c +++ b/arch/x86/stage1.c @@ -37,6 +37,7 @@ void uart_init(void); void die(const char *msg); void hardware_stage1(void); void disable_car(void); +void mainboard_pre_payload(void); static void stop_ap(void) { @@ -177,11 +178,13 @@ void __attribute__((stdcall)) stage1_main(u32 bist) legacy(&archive, "normal/payload", (void *)UNCOMPRESS_AREA, mem); entry = load_file_segments(&archive, "normal/payload"); - if (entry != (void*)-1) + if (entry != (void*)-1) { + /* Final coreboot call before handing off to the payload. */ + mainboard_pre_payload(); run_address(entry); - else + } else { die("FATAL: No usable payload found.\n"); - + } die ("FATAL: Last stage returned to coreboot.\n"); } diff --git a/include/arch/x86/amd_geodelx.h b/include/arch/x86/amd_geodelx.h index c24c1595be..695180b7b7 100644 --- a/include/arch/x86/amd_geodelx.h +++ b/include/arch/x86/amd_geodelx.h @@ -1269,6 +1269,7 @@ void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo); void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1); void system_preinit(void); void msr_init(void); +void geode_pre_payload(void); #endif #endif diff --git a/mainboard/adl/msm800sev/stage1.c b/mainboard/adl/msm800sev/stage1.c index 1c758ae9ce..b27a997ea4 100644 --- a/mainboard/adl/msm800sev/stage1.c +++ b/mainboard/adl/msm800sev/stage1.c @@ -53,3 +53,9 @@ void hardware_stage1(void) cs5536_disable_internal_uart(); w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); } + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} diff --git a/mainboard/amd/norwich/stage1.c b/mainboard/amd/norwich/stage1.c index 3f0724875a..94cffe3905 100644 --- a/mainboard/amd/norwich/stage1.c +++ b/mainboard/amd/norwich/stage1.c @@ -46,3 +46,9 @@ void hardware_stage1(void) */ cs5536_setup_onchipuart(); } + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} diff --git a/mainboard/artecgroup/dbe61/stage1.c b/mainboard/artecgroup/dbe61/stage1.c index 600fd868a0..b24d4b9413 100644 --- a/mainboard/artecgroup/dbe61/stage1.c +++ b/mainboard/artecgroup/dbe61/stage1.c @@ -61,3 +61,9 @@ void hardware_stage1(void) */ cs5536_setup_onchipuart(); } + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} diff --git a/mainboard/emulation/qemu-x86/stage1.c b/mainboard/emulation/qemu-x86/stage1.c index 225363b79f..c68727631c 100644 --- a/mainboard/emulation/qemu-x86/stage1.c +++ b/mainboard/emulation/qemu-x86/stage1.c @@ -30,3 +30,8 @@ void hardware_stage1(void) void disable_car(void) { } + + +void pre_payload(void) +{ +} diff --git a/mainboard/pcengines/alix1c/stage1.c b/mainboard/pcengines/alix1c/stage1.c index 3ad14f3a78..bbcf7d3e9e 100644 --- a/mainboard/pcengines/alix1c/stage1.c +++ b/mainboard/pcengines/alix1c/stage1.c @@ -49,3 +49,9 @@ void hardware_stage1(void) w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); } + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} diff --git a/northbridge/amd/geodelx/geodelxinit.c b/northbridge/amd/geodelx/geodelxinit.c index 6df94fa0e7..69549615e7 100644 --- a/northbridge/amd/geodelx/geodelxinit.c +++ b/northbridge/amd/geodelx/geodelxinit.c @@ -658,7 +658,8 @@ static void rom_shadow_settings(void) #define SYSMEM_RCONF_WRITETHROUGH 8 #define DEVRC_RCONF_DEFAULT 0x21 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000 -#define ROMRC_RCONF_DEFAULT 0x25 +#define ROMRC_RCONF_SAFE 0x25 +#define ROMRC_RCONF_DEFAULT 0x04 /** * TODO. @@ -848,3 +849,15 @@ void northbridge_init_early(void) printk(BIOS_DEBUG, "Exit %s\n", __FUNCTION__); } + +void geode_pre_payload(void) +{ + struct msr msr; + + /* Set ROM cache properties for runtime. */ + msr = rdmsr(CPU_RCONF_DEFAULT); + msr.hi &= ~(0xFF << 24); // clear ROMRC + msr.hi |= ROMRC_RCONF_SAFE << 24; // set WS, CD, WP + wrmsr(CPU_RCONF_DEFAULT, msr); +} + diff --git a/util/lar/lar.h b/util/lar/lar.h index 7331f146f0..b5d67d0d6e 100644 --- a/util/lar/lar.h +++ b/util/lar/lar.h @@ -52,7 +52,7 @@ #define MAGIC "LARCHIVE" #define MAX_PATHLEN 1024 -#define BOOTBLOCK_SIZE 16384 +#define BOOTBLOCK_SIZE 20480 #define BOOTBLOCK_NAME "bootblock" #define BOOTBLOCK_NAME_LEN 16