mirror of
https://github.com/fail0verflow/switch-coreboot.git
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Adding pci irq support. Yuck.
This commit is contained in:
Ronald G. Minnich
parent
4355f389e2
commit
56a01c28dc
1 changed files with 753 additions and 0 deletions
753
src/lib/pci-irq.c
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753
src/lib/pci-irq.c
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@ -0,0 +1,753 @@
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/*
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* Low-Level PCI Support for PC -- Routing of Interrupts
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*
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/io_apic.h>
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#include "pci-i386.h"
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#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
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#define PIRQ_VERSION 0x0100
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static struct irq_routing_table *pirq_table;
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/*
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* Never use: 0, 1, 2 (timer, keyboard, and cascade)
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* Avoid using: 13, 14 and 15 (FP error and IDE).
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* Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
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*/
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unsigned int pcibios_irq_mask = 0xfff8;
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static int pirq_penalty[16] = {
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1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
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0, 0, 0, 0, 1000, 100000, 100000, 100000
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};
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struct irq_router {
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char *name;
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u16 vendor, device;
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int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
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int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
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};
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/*
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* Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
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*/
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static struct irq_routing_table * __init pirq_find_routing_table(void)
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{
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u8 *addr;
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struct irq_routing_table *rt;
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int i;
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u8 sum;
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for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
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rt = (struct irq_routing_table *) addr;
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if (rt->signature != PIRQ_SIGNATURE ||
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rt->version != PIRQ_VERSION ||
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rt->size % 16 ||
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rt->size < sizeof(struct irq_routing_table))
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continue;
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sum = 0;
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for(i=0; i<rt->size; i++)
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sum += addr[i];
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if (!sum) {
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DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
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return rt;
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}
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}
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return NULL;
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}
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/*
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* If we have a IRQ routing table, use it to search for peer host
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* bridges. It's a gross hack, but since there are no other known
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* ways how to get a list of buses, we have to go this way.
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*/
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static void __init pirq_peer_trick(void)
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{
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struct irq_routing_table *rt = pirq_table;
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u8 busmap[256];
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int i;
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struct irq_info *e;
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memset(busmap, 0, sizeof(busmap));
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for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
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e = &rt->slots[i];
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#ifdef DEBUG
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{
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int j;
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DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
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for(j=0; j<4; j++)
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DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
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DBG("\n");
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}
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#endif
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busmap[e->bus] = 1;
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}
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for(i=1; i<256; i++)
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/*
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* It might be a secondary bus, but in this case its parent is already
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* known (ascending bus order) and therefore pci_scan_bus returns immediately.
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*/
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if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL))
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printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
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pcibios_last_bus = -1;
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}
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/*
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* Code for querying and setting of IRQ routes on various interrupt routers.
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*/
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static void eisa_set_level_irq(unsigned int irq)
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{
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unsigned char mask = 1 << (irq & 7);
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unsigned int port = 0x4d0 + (irq >> 3);
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unsigned char val = inb(port);
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if (!(val & mask)) {
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DBG(" -> edge");
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outb(val | mask, port);
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}
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}
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/*
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* Common IRQ routing practice: nybbles in config space,
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* offset by some magic constant.
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*/
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static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
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{
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u8 x;
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unsigned reg = offset + (nr >> 1);
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pci_read_config_byte(router, reg, &x);
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return (nr & 1) ? (x >> 4) : (x & 0xf);
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}
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static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
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{
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u8 x;
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unsigned reg = offset + (nr >> 1);
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pci_read_config_byte(router, reg, &x);
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x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
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pci_write_config_byte(router, reg, x);
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}
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/*
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* ALI pirq entries are damn ugly, and completely undocumented.
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* This has been figured out from pirq tables, and it's not a pretty
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* picture.
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*/
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static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
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return irqmap[read_config_nybble(router, 0x48, pirq-1)];
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}
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static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
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unsigned int val = irqmap[irq];
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if (val) {
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write_config_nybble(router, 0x48, pirq-1, val);
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return 1;
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}
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return 0;
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}
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/*
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* The Intel PIIX4 pirq rules are fairly simple: "pirq" is
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* just a pointer to the config space.
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*/
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static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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u8 x;
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pci_read_config_byte(router, pirq, &x);
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return (x < 16) ? x : 0;
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}
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static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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pci_write_config_byte(router, pirq, irq);
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return 1;
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}
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/*
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* The VIA pirq rules are nibble-based, like ALI,
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* but without the ugly irq number munging.
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*/
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static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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return read_config_nybble(router, 0x55, pirq);
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}
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static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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write_config_nybble(router, 0x55, pirq, irq);
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return 1;
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}
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/*
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* OPTI: high four bits are nibble pointer..
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* I wonder what the low bits do?
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*/
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static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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return read_config_nybble(router, 0xb8, pirq >> 4);
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}
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static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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write_config_nybble(router, 0xb8, pirq >> 4, irq);
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return 1;
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}
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/*
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* Cyrix: nibble offset 0x5C
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*/
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static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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return read_config_nybble(router, 0x5C, pirq-1);
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}
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static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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write_config_nybble(router, 0x5C, pirq-1, irq);
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return 1;
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}
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/*
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* PIRQ routing for SiS 85C503 router used in several SiS chipsets
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* According to the SiS 5595 datasheet (preliminary V1.0, 12/24/1997)
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* the related registers work as follows:
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*
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* general: one byte per re-routable IRQ,
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* bit 7 IRQ mapping enabled (0) or disabled (1)
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* bits [6:4] reserved
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* bits [3:0] IRQ to map to
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* allowed: 3-7, 9-12, 14-15
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* reserved: 0, 1, 2, 8, 13
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*
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* individual registers in device config space:
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*
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* 0x41/0x42/0x43/0x44: PCI INT A/B/C/D - bits as in general case
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*
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* 0x61: IDEIRQ: bits as in general case - but:
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* bits [6:5] must be written 01
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* bit 4 channel-select primary (0), secondary (1)
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*
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* 0x62: USBIRQ: bits as in general case - but:
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* bit 4 OHCI function disabled (0), enabled (1)
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*
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* 0x6a: ACPI/SCI IRQ - bits as in general case
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*
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* 0x7e: Data Acq. Module IRQ - bits as in general case
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*
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* Apparently there are systems implementing PCI routing table using both
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* link values 0x01-0x04 and 0x41-0x44 for PCI INTA..D, but register offsets
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* like 0x62 as link values for USBIRQ e.g. So there is no simple
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* "register = offset + pirq" relation.
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* Currently we support PCI INTA..D and USBIRQ and try our best to handle
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* both link mappings.
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* IDE/ACPI/DAQ mapping is currently unsupported (left untouched as set by BIOS).
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*/
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static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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u8 x;
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int reg = pirq;
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switch(pirq) {
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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reg += 0x40;
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x62:
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pci_read_config_byte(router, reg, &x);
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if (reg != 0x62)
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break;
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if (!(x & 0x40))
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return 0;
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break;
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case 0x61:
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case 0x6a:
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case 0x7e:
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printk(KERN_INFO "SiS pirq: advanced IDE/ACPI/DAQ mapping not yet implemented\n");
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return 0;
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default:
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printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq);
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return 0;
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}
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return (x & 0x80) ? 0 : (x & 0x0f);
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}
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static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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u8 x;
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int reg = pirq;
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switch(pirq) {
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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reg += 0x40;
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x62:
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x = (irq&0x0f) ? (irq&0x0f) : 0x80;
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if (reg != 0x62)
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break;
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/* always mark OHCI enabled, as nothing else knows about this */
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x |= 0x40;
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break;
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case 0x61:
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case 0x6a:
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case 0x7e:
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printk(KERN_INFO "advanced SiS pirq mapping not yet implemented\n");
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return 0;
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default:
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printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq);
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return 0;
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}
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pci_write_config_byte(router, reg, x);
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return 1;
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}
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/*
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* VLSI: nibble offset 0x74 - educated guess due to routing table and
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* config space of VLSI 82C534 PCI-bridge/router (1004:0102)
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* Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
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* devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
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* for the busbridge to the docking station.
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*/
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static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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if (pirq > 8) {
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printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
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return 0;
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}
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return read_config_nybble(router, 0x74, pirq-1);
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}
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static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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if (pirq > 8) {
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printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
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return 0;
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}
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write_config_nybble(router, 0x74, pirq-1, irq);
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return 1;
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}
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/*
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* ServerWorks: PCI interrupts mapped to system IRQ lines through Index
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* and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
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* format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
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* register is a straight binary coding of desired PIC IRQ (low nibble).
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*
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* The 'link' value in the PIRQ table is already in the correct format
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* for the Index register. There are some special index values:
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* 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
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* and 0x03 for SMBus.
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*/
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static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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outb_p(pirq, 0xc00);
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return inb(0xc01) & 0xf;
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}
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static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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outb_p(pirq, 0xc00);
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outb_p(irq, 0xc01);
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return 1;
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}
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/* Support for AMD756 PCI IRQ Routing
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* Jhon H. Caicedo <jhcaiced@osso.org.co>
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* Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
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* Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
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* The AMD756 pirq rules are nibble-based
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* offset 0x56 0-3 PIRQA 4-7 PIRQB
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* offset 0x57 0-3 PIRQC 4-7 PIRQD
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*/
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static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
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{
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u8 irq;
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irq = 0;
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if (pirq <= 4)
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{
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irq = read_config_nybble(router, 0x56, pirq - 1);
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}
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printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
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dev->vendor, dev->device, pirq, irq);
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return irq;
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}
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static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
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dev->vendor, dev->device, pirq, irq);
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if (pirq <= 4)
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{
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write_config_nybble(router, 0x56, pirq - 1, irq);
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}
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return 1;
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}
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#ifdef CONFIG_PCI_BIOS
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static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
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{
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struct pci_dev *bridge;
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int pin = pci_get_interrupt_pin(dev, &bridge);
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return pcibios_set_irq_routing(bridge, pin, irq);
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}
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static struct irq_router pirq_bios_router =
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{ "BIOS", 0, 0, NULL, pirq_bios_set };
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#endif
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static struct irq_router pirq_routers[] = {
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{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, pirq_piix_get, pirq_piix_set },
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{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, pirq_piix_get, pirq_piix_set },
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{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, pirq_piix_get, pirq_piix_set },
|
||||
{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, pirq_piix_get, pirq_piix_set },
|
||||
{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_0, pirq_piix_get, pirq_piix_set },
|
||||
{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, pirq_piix_get, pirq_piix_set },
|
||||
|
||||
{ "ALI", PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, pirq_ali_get, pirq_ali_set },
|
||||
|
||||
{ "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, pirq_via_get, pirq_via_set },
|
||||
{ "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, pirq_via_get, pirq_via_set },
|
||||
{ "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, pirq_via_get, pirq_via_set },
|
||||
|
||||
{ "OPTI", PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C700, pirq_opti_get, pirq_opti_set },
|
||||
|
||||
{ "NatSemi", PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, pirq_cyrix_get, pirq_cyrix_set },
|
||||
{ "SIS", PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, pirq_sis_get, pirq_sis_set },
|
||||
{ "VLSI 82C534", PCI_VENDOR_ID_VLSI, PCI_DEVICE_ID_VLSI_82C534, pirq_vlsi_get, pirq_vlsi_set },
|
||||
{ "ServerWorks", PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4,
|
||||
pirq_serverworks_get, pirq_serverworks_set },
|
||||
{ "ServerWorks", PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5,
|
||||
pirq_serverworks_get, pirq_serverworks_set },
|
||||
{ "AMD756 VIPER", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B,
|
||||
pirq_amd756_get, pirq_amd756_set },
|
||||
|
||||
{ "default", 0, 0, NULL, NULL }
|
||||
};
|
||||
|
||||
static struct irq_router *pirq_router;
|
||||
static struct pci_dev *pirq_router_dev;
|
||||
|
||||
static void __init pirq_find_router(void)
|
||||
{
|
||||
struct irq_routing_table *rt = pirq_table;
|
||||
struct irq_router *r;
|
||||
|
||||
#ifdef CONFIG_PCI_BIOS
|
||||
if (!rt->signature) {
|
||||
printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
|
||||
pirq_router = &pirq_bios_router;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
|
||||
rt->rtr_vendor, rt->rtr_device);
|
||||
|
||||
/* fall back to default router if nothing else found */
|
||||
pirq_router = &pirq_routers[ARRAY_SIZE(pirq_routers) - 1];
|
||||
|
||||
pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
|
||||
if (!pirq_router_dev) {
|
||||
DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
|
||||
return;
|
||||
}
|
||||
|
||||
for(r=pirq_routers; r->vendor; r++) {
|
||||
/* Exact match against router table entry? Use it! */
|
||||
if (r->vendor == rt->rtr_vendor && r->device == rt->rtr_device) {
|
||||
pirq_router = r;
|
||||
break;
|
||||
}
|
||||
/* Match against router device entry? Use it as a fallback */
|
||||
if (r->vendor == pirq_router_dev->vendor && r->device == pirq_router_dev->device) {
|
||||
pirq_router = r;
|
||||
}
|
||||
}
|
||||
printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
|
||||
pirq_router->name,
|
||||
pirq_router_dev->vendor,
|
||||
pirq_router_dev->device,
|
||||
pirq_router_dev->slot_name);
|
||||
}
|
||||
|
||||
static struct irq_info *pirq_get_info(struct pci_dev *dev)
|
||||
{
|
||||
struct irq_routing_table *rt = pirq_table;
|
||||
int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
|
||||
struct irq_info *info;
|
||||
|
||||
for (info = rt->slots; entries--; info++)
|
||||
if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
|
||||
return info;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void pcibios_test_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
}
|
||||
|
||||
static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
|
||||
{
|
||||
u8 pin;
|
||||
struct irq_info *info;
|
||||
int i, pirq, newirq;
|
||||
int irq = 0;
|
||||
u32 mask;
|
||||
struct irq_router *r = pirq_router;
|
||||
struct pci_dev *dev2;
|
||||
char *msg = NULL;
|
||||
|
||||
if (!pirq_table)
|
||||
return 0;
|
||||
|
||||
/* Find IRQ routing entry */
|
||||
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
|
||||
if (!pin) {
|
||||
DBG(" -> no interrupt pin\n");
|
||||
return 0;
|
||||
}
|
||||
pin = pin - 1;
|
||||
|
||||
DBG("IRQ for %s:%d", dev->slot_name, pin);
|
||||
info = pirq_get_info(dev);
|
||||
if (!info) {
|
||||
DBG(" -> not found in routing table\n");
|
||||
return 0;
|
||||
}
|
||||
pirq = info->irq[pin].link;
|
||||
mask = info->irq[pin].bitmap;
|
||||
if (!pirq) {
|
||||
DBG(" -> not routed\n");
|
||||
return 0;
|
||||
}
|
||||
DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
|
||||
mask &= pcibios_irq_mask;
|
||||
|
||||
/*
|
||||
* Find the best IRQ to assign: use the one
|
||||
* reported by the device if possible.
|
||||
*/
|
||||
newirq = dev->irq;
|
||||
if (!newirq && assign) {
|
||||
for (i = 0; i < 16; i++) {
|
||||
if (!(mask & (1 << i)))
|
||||
continue;
|
||||
if (pirq_penalty[i] < pirq_penalty[newirq] &&
|
||||
!request_irq(i, pcibios_test_irq_handler, SA_SHIRQ, "pci-test", dev)) {
|
||||
free_irq(i, dev);
|
||||
newirq = i;
|
||||
}
|
||||
}
|
||||
}
|
||||
DBG(" -> newirq=%d", newirq);
|
||||
|
||||
/* Check if it is hardcoded */
|
||||
if ((pirq & 0xf0) == 0xf0) {
|
||||
irq = pirq & 0xf;
|
||||
DBG(" -> hardcoded IRQ %d\n", irq);
|
||||
msg = "Hardcoded";
|
||||
} else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq))) {
|
||||
DBG(" -> got IRQ %d\n", irq);
|
||||
msg = "Found";
|
||||
} else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
|
||||
DBG(" -> assigning IRQ %d", newirq);
|
||||
if (r->set(pirq_router_dev, dev, pirq, newirq)) {
|
||||
eisa_set_level_irq(newirq);
|
||||
DBG(" ... OK\n");
|
||||
msg = "Assigned";
|
||||
irq = newirq;
|
||||
}
|
||||
}
|
||||
|
||||
if (!irq) {
|
||||
DBG(" ... failed\n");
|
||||
if (newirq && mask == (1 << newirq)) {
|
||||
msg = "Guessed";
|
||||
irq = newirq;
|
||||
} else
|
||||
return 0;
|
||||
}
|
||||
printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, dev->slot_name);
|
||||
|
||||
/* Update IRQ for all devices with the same pirq value */
|
||||
pci_for_each_dev(dev2) {
|
||||
pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
|
||||
if (!pin)
|
||||
continue;
|
||||
pin--;
|
||||
info = pirq_get_info(dev2);
|
||||
if (!info)
|
||||
continue;
|
||||
if (info->irq[pin].link == pirq) {
|
||||
/* We refuse to override the dev->irq information. Give a warning! */
|
||||
if (dev2->irq && dev2->irq != irq) {
|
||||
printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
|
||||
dev2->slot_name, dev2->irq, irq);
|
||||
continue;
|
||||
}
|
||||
dev2->irq = irq;
|
||||
pirq_penalty[irq]++;
|
||||
if (dev != dev2)
|
||||
printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, dev2->slot_name);
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
void __init pcibios_irq_init(void)
|
||||
{
|
||||
DBG("PCI: IRQ init\n");
|
||||
pirq_table = pirq_find_routing_table();
|
||||
//#ifdef CONFIG_PCI_BIOS
|
||||
if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
|
||||
pirq_table = pcibios_get_irq_routing_table();
|
||||
//#endif
|
||||
DBG("pirq table is %p\n", pirq_table);
|
||||
if (pirq_table) {
|
||||
pirq_peer_trick();
|
||||
pirq_find_router();
|
||||
if (pirq_table->exclusive_irqs) {
|
||||
int i;
|
||||
for (i=0; i<16; i++)
|
||||
if (!(pirq_table->exclusive_irqs & (1 << i)))
|
||||
pirq_penalty[i] += 100;
|
||||
}
|
||||
/* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
|
||||
if (io_apic_assign_pci_irqs)
|
||||
pirq_table = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
void __init pcibios_fixup_irqs(void)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
u8 pin;
|
||||
|
||||
DBG("PCI: IRQ fixup\n");
|
||||
pci_for_each_dev(dev) {
|
||||
/*
|
||||
* If the BIOS has set an out of range IRQ number, just ignore it.
|
||||
* Also keep track of which IRQ's are already in use.
|
||||
*/
|
||||
if (dev->irq >= 16) {
|
||||
DBG("%s: ignoring bogus IRQ %d\n", dev->slot_name, dev->irq);
|
||||
dev->irq = 0;
|
||||
}
|
||||
/* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
|
||||
if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
|
||||
pirq_penalty[dev->irq] = 0;
|
||||
pirq_penalty[dev->irq]++;
|
||||
}
|
||||
|
||||
pci_for_each_dev(dev) {
|
||||
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
/*
|
||||
* Recalculate IRQ numbers if we use the I/O APIC.
|
||||
*/
|
||||
if (io_apic_assign_pci_irqs)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (pin) {
|
||||
pin--; /* interrupt pins are numbered starting from 1 */
|
||||
irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
|
||||
/*
|
||||
* Busses behind bridges are typically not listed in the MP-table.
|
||||
* In this case we have to look up the IRQ based on the parent bus,
|
||||
* parent slot, and pin number. The SMP code detects such bridged
|
||||
* busses itself so we should get into this branch reliably.
|
||||
*/
|
||||
if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
|
||||
struct pci_dev * bridge = dev->bus->self;
|
||||
|
||||
pin = (pin + PCI_SLOT(dev->devfn)) % 4;
|
||||
irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
|
||||
PCI_SLOT(bridge->devfn), pin);
|
||||
if (irq >= 0)
|
||||
printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
|
||||
bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
|
||||
}
|
||||
if (irq >= 0) {
|
||||
printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
|
||||
dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
|
||||
dev->irq = irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Still no IRQ? Try to lookup one...
|
||||
*/
|
||||
if (pin && !dev->irq)
|
||||
pcibios_lookup_irq(dev, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void pcibios_penalize_isa_irq(int irq)
|
||||
{
|
||||
/*
|
||||
* If any ISAPnP device reports an IRQ in its list of possible
|
||||
* IRQ's, we try to avoid assigning it to PCI devices.
|
||||
*/
|
||||
pirq_penalty[irq] += 100;
|
||||
}
|
||||
|
||||
void pcibios_enable_irq(struct pci_dev *dev)
|
||||
{
|
||||
u8 pin;
|
||||
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
|
||||
if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
|
||||
char *msg;
|
||||
if (io_apic_assign_pci_irqs)
|
||||
msg = " Probably buggy MP table.";
|
||||
else if (pci_probe & PCI_BIOS_IRQ_SCAN)
|
||||
msg = "";
|
||||
else
|
||||
msg = " Please try using pci=biosirq.";
|
||||
printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
|
||||
'A' + pin - 1, dev->slot_name, msg);
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue