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intel/skylake: Remove check for Microcode loaded by ME
This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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1 changed files with 1 additions and 22 deletions
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@ -171,32 +171,11 @@ static void check_for_clean_reset(void)
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soft_reset();
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soft_reset();
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}
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}
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static void patch_microcode(void)
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{
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const struct microcode *patch;
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u32 current_rev;
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msr_t msr;
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patch = intel_microcode_find();
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current_rev = read_microcode_rev();
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/* If PRMRR/SGX is supported the FIT microcode load step will set
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* msr 0x08b with the Patch revision id one less than the id in the
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* microcode binary. The PRMRR support is indicated in the MSR
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* MTRRCAP[12]. Check for this feature and avoid reloading the
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* same microcode during early cpu initialization.
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*/
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msr = rdmsr(MTRR_CAP_MSR);
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if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1))
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intel_update_microcode_from_cbfs();
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}
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static void bootblock_cpu_init(void)
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static void bootblock_cpu_init(void)
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{
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{
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/* Set flex ratio and reset if needed */
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/* Set flex ratio and reset if needed */
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set_flex_ratio_to_tdp_nominal();
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set_flex_ratio_to_tdp_nominal();
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check_for_clean_reset();
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check_for_clean_reset();
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enable_rom_caching();
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enable_rom_caching();
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patch_microcode();
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intel_update_microcode_from_cbfs();
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}
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}
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