diff --git a/Makefile b/Makefile index 865b64f29b..0531d18433 100644 --- a/Makefile +++ b/Makefile @@ -81,8 +81,8 @@ MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_NAME)) include lib/Makefile include device/Makefile include console/Makefile -include arch/$(ARCH)/Makefile include mainboard/$(MAINBOARDDIR)/Makefile +include arch/$(ARCH)/Makefile endif include util/Makefile diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 6de41680b8..4c7c651a30 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -115,7 +115,7 @@ STAGE2_MAINBOARD_OBJ = $(obj)/mainboard.o STAGE2_DYNAMIC_OBJ = $(obj)/statictree.o STAGE2_OBJ := $(STAGE2_LIB_OBJ) $(STAGE2_DEVICE_OBJ) $(STAGE2_ARCH_X86_OBJ) -STAGE2_OBJ += $(STAGE2_MAINBOARD_OBJ) $(STAGE2_DYNAMIC_OBJ) +STAGE2_OBJ += $(STAGE2_MAINBOARD_OBJ) $(STAGE2_DYNAMIC_OBJ) $(STAGE2_CHIPSET_OBJ) $(obj)/linuxbios.stage2: $(obj)/stage0.init $(STAGE2_OBJ) $(Q)printf "Building linuxbios.stage2... " diff --git a/mainboard/emulation/qemu-i386/Kconfig b/mainboard/emulation/qemu-i386/Kconfig index bea7e4950c..decbab79b5 100644 --- a/mainboard/emulation/qemu-i386/Kconfig +++ b/mainboard/emulation/qemu-i386/Kconfig @@ -5,3 +5,4 @@ config MAINBOARD_NAME help This is the default mainboard name. +source northbridge/intel/i440bxemulation/Kconfig \ No newline at end of file diff --git a/mainboard/emulation/qemu-i386/Makefile b/mainboard/emulation/qemu-i386/Makefile index a96a57f7bc..a31365cb07 100644 --- a/mainboard/emulation/qemu-i386/Makefile +++ b/mainboard/emulation/qemu-i386/Makefile @@ -57,4 +57,8 @@ $(obj)/statictree.o: $(obj)/statictree.c $(obj)/statictree.c: mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc $(Q)$(obj)/util/dtc/dtc -O lb mainboard/$(MAINBOARDDIR)/dts >$(obj)/statictree.c 2>/dev/null +STAGE2_CHIPSET_OBJ = +# chipset +include $(src)/northbridge/intel/i440bxemulation/Makefile + diff --git a/mainboard/emulation/qemu-i386/dts b/mainboard/emulation/qemu-i386/dts index 883198a642..d710fdf5d1 100644 --- a/mainboard/emulation/qemu-i386/dts +++ b/mainboard/emulation/qemu-i386/dts @@ -11,6 +11,7 @@ /* the I/O stuff */ northbridge,intel,440bx{ + config="northbridge,intel,i440bxemulation"; pcipath = "0,0"; southbridge,intel,piix4{ }; @@ -28,3 +29,6 @@ struct mainboard_emulation_qemu_i386_config root = { }; +struct northbridge_intel_i440bx_config northbridge_intel_440bx = { + .ramsize = CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE, +}; \ No newline at end of file diff --git a/northbridge/intel/i440bxemulation/Kconfig b/northbridge/intel/i440bxemulation/Kconfig new file mode 100644 index 0000000000..06f1f3c916 --- /dev/null +++ b/northbridge/intel/i440bxemulation/Kconfig @@ -0,0 +1,6 @@ +config NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE + int + default 32 # Mbytes + help + This is the default ram size of emulation + diff --git a/northbridge/intel/i440bxemulation/Makefile b/northbridge/intel/i440bxemulation/Makefile new file mode 100644 index 0000000000..63299fac8b --- /dev/null +++ b/northbridge/intel/i440bxemulation/Makefile @@ -0,0 +1,29 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# I think a .c.o rule might be more confusing than just putting the rule +# underneath the dependency graph -- but I welcome correction on this. + +$(obj)/i440bx.o: $(src)/northbridge/intel/i440bxemulation/i440bx.c + $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ + + +STAGE2_CHIPSET_OBJ += $(obj)/i440bx.o + diff --git a/northbridge/intel/i440bxemulation/config.h b/northbridge/intel/i440bxemulation/config.h new file mode 100644 index 0000000000..0486bc8fb3 --- /dev/null +++ b/northbridge/intel/i440bxemulation/config.h @@ -0,0 +1,31 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations northbridge_intel_i440bxemulation_ops; + +struct northbridge_intel_i440bx_config +{ + /* the various emulators don't always get 440bx right. So we are going to allow + * users to set the ramsize via Kconfig. + */ + int ramsize; +}; + diff --git a/northbridge/intel/i440bxemulation/i440bx.c b/northbridge/intel/i440bxemulation/i440bx.c new file mode 100644 index 0000000000..dce466c7a7 --- /dev/null +++ b/northbridge/intel/i440bxemulation/i440bx.c @@ -0,0 +1,46 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "config.h" +#include "i440bx.h" + +/* this is the starting point */ + +static void i440bxemulation_enable_dev(struct device *dev) +{ + printk(BIOS_INFO, "%s: \n", __FUNCTION__); + /* Set the operations if it is a special bus type */ +/* + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } + */ +} + +struct chip_operations northbridge_intel_i440bxemulation_ops = { + .name="Intel 440BX Northbridge Emulation", + .enable_dev = i440bxemulation_enable_dev, +}; diff --git a/northbridge/intel/i440bxemulation/i440bx.h b/northbridge/intel/i440bxemulation/i440bx.h new file mode 100644 index 0000000000..5e2679e93f --- /dev/null +++ b/northbridge/intel/i440bxemulation/i440bx.h @@ -0,0 +1,90 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller + * - URL: http://www.intel.com/design/chipsets/datashts/290633.htm + * - PDF: http://www.intel.com/design/chipsets/datashts/29063301.pdf + * - Order Number: 290633-001 + */ + +/* + * Host-to-PCI Bridge Registers. + * The values in parenthesis are the default values as per datasheet. + * Any addresses between 0x00 and 0xff not listed below are either + * Reserved or Intel Reserved and should not be touched. + */ +#define VID 0x00 /* Vendor Identification (0x8086). */ +#define DID 0x02 /* Device Identification (0x7190/0x7192). */ +#define PCICMD 0x04 /* PCI Command Register (0x006). */ +#define PCISTS 0x06 /* PCI Status Register (0x0210/0x0200). */ +#define RID 0x08 /* Revision Identification (0x00/0x01/0x02). */ +#define SUBC 0x0a /* Sub-Class Code (0x00). */ +#define BCC 0x0b /* Base Class Code (0x06). */ +#define MLT 0x0d /* Master Latency Timer (0x00). */ +#define HDR 0x0e /* Header Type (0x00). */ +#define APBASE 0x10 /* Aperture Base Configuration (0x00000008). */ +#define SVID 0x2c /* Subsystem Vendor Identification (0x0000). */ +#define SID 0x2e /* Subsystem Identification (0x0000). */ +#define CAPPTR 0x34 /* Capabilities Pointer (0xa0/0x00). */ +#define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */ +#define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ +#define DRAMT 0x58 /* DRAM Timing (0x03). */ +#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ +#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ +#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ +#define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */ +#define SMRAM 0x72 /* System Management RAM Control (0x02). */ +#define ESMRAMC 0x73 /* Extended System Management RAM Control (0x38). */ +#define RPS 0x74 /* SDRAM Row Page Size (0x0000). */ +#define SDRAMC 0x76 /* SDRAM Control Register (0x0000). */ +#define PGPOL 0x78 /* Paging Policy Register (0x00). */ +#define PMCR 0x7a /* Power Management Control Register (0000_S0S0b). */ +#define SCRR 0x7b /* Suspend CBR Refresh Rate Register (0x0038). */ +#define EAP 0x80 /* Error Address Pointer Register (0x00000000). */ +#define ERRCMD 0x90 /* Error Command Register (0x80). */ +#define ERRSTS 0x91 /* Error Status (0x0000). */ +// TODO: AGP stuff. +#define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ +#define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ +#define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ +#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ +#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ + +/* For convenience: */ +#define DRB0 0x60 +#define DRB1 0x61 +#define DRB2 0x62 +#define DRB3 0x63 +#define DRB4 0x64 +#define DRB5 0x65 +#define DRB6 0x66 +#define DRB7 0x67 + +#define PAM0 0x59 +#define PAM1 0x5a +#define PAM2 0x5b +#define PAM3 0x5c +#define PAM4 0x5d +#define PAM5 0x5e +#define PAM6 0x5f + +unsigned int i440bx_scan_root_bus(struct device * root, unsigned int max);