mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
smartcore p5 support.
This commit is contained in:
Ronald G. Minnich
parent
402332c59c
commit
523a37fb8f
2 changed files with 373 additions and 94 deletions
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@ -1,20 +1,29 @@
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# Sample config file for digital logic smartcore-p5
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# Sample config file for Intel 430TX chipset on the Smartcore P5
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# This will make a target directory of ./smartcore-p5
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target smartcore-p5
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# ASUS CUA main board
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mainboard digitallogic/smartcore-p5
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# option HAVE_PIRQ_TABLE=1
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE=1
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option NO_KEYBOARD
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option INBUF_COPY
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option DEFAULT_CONSOLE_LOGLEVEL=9
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option DEBUG
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option USE_GENERIC_ROM=1
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# MEMORY TESTING USING MEMTEST
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option USE_ELF_BOOT=1
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# *****************MODIFIED BY BHARATH********************
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# Path to your kernel (vmlinux)
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linux ~/src/bios/linux-2.4.7-sis
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linux /users/bxmx/kernels/vmlinux-2.4.14
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# Kernel command line parameters
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commandline root=/dev/hda6 console=ttyS0,115200 FS_MODE=ro hda=flash hdb=flash
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# *******************MODIFIED BY BHARATH ****************
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commandline root=/dev/hdc2 console=ttyS0,115200 floppy=nodma single
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option RAMTEST
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@ -1,5 +1,26 @@
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jmp intel_430_out
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/* **** Bharath's debugging crap *********** */
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after_enable_smbus: .string "After enable_smbus\r\n"
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after_setup_smbus: .string "After setup_smbus\r\n"
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after_configure_sdramc: .string "After configure_sdramc\r\n"
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after_configure_drb: .string "After configure_drb\r\n"
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before_pci_read: .string "Before PCI Read\r\n"
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after_pci_read: .string "After PCI Read\r\n"
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before_mem_read: .string "Before 0x0400 Read\r\n"
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after_mem_read: .string "After 0x0400 Read\r\n"
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north_bridge_error: .string "OOps, can't write to PAM registers properly\r\n"
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after_zero: .string "After 0x00...\r\n"
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before_zero_nop: .string "Before 0x0000000 nop...\r\n"
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after_zero_nop: .string "After 0x0000000 nop...\r\n"
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after_one_million: .string "After 0x0000000...\r\n"
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after_fifty_four: .string "After 0x54...\r\n"
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firsttime: .string "First DRAM setup done\r\n"
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secondtime: .string "Second DRAM setup done\r\n"
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/* **** End Bharath's debugging crap **** */
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#define USE_SPD 1
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#define CS_WRITE_BYTE(addr, byte) \
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@ -18,7 +39,12 @@ jmp intel_430_out
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PCI_WRITE_CONFIG_DWORD
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/* Default memory set to 0 */
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#define DRB 0x00
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#define DRB0 0x10
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#define DRB1 0x20
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#define DRB2 0x20
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#define DRB3 0x20
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#define DRB4 0x20
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#define DRB5 0x20
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/* The DRB register for the first row */
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#define DRB_REG0 $0x60
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@ -32,19 +58,23 @@ jmp intel_430_out
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xorl %eax, %eax
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#define DIMM_BASE(n) \
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movl $(0x60 + ((n) -1)), %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0xFF, %eax ; \
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shll $22, %eax ; /* 4 MB granularity for the 430TX */
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// CONSOLE_DEBUG_TX_STRING($before_pci_read) ; \
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// movl n, %eax ; \
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// PCI_READ_CONFIG_BYTE ; \
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// CONSOLE_DEBUG_TX_STRING($after_pci_read) ; \
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// andl $0xFF, %eax ; \
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// shll $22, %eax ; /* 4 MB granularity for the 430TX */
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#define DIMM_READ \
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addl %ebx, %eax ; \
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movl (%eax), %edx ; \
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xorl $0xdff8, %eax ; \
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movl (%eax), %edx
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// addl %ebx, %eax ; \
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// CONSOLE_DEBUG_TX_STRING($before_mem_read) ; \
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// movl (%eax), %edx ;
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// CONSOLE_DEBUG_TX_STRING($after_mem_read) ; \
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// xorl $0xdff8, %eax ; \
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// movl (%eax), %edx
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#define DIMM0_READ DIMM0_BASE ; DIMM_READ
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#define DIMM1_READ DIMM_BASE(1) ; DIMM_READ
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#define DIMM1_READ DIMM_BASE($0x60) ; DIMM_READ
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#define DIMM2_READ DIMM_BASE(2) ; DIMM_READ
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#define DIMM3_READ DIMM_BASE(3) ; DIMM_READ
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#define DIMM4_READ DIMM_BASE(4) ; DIMM_READ
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@ -52,110 +82,320 @@ jmp intel_430_out
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#define DIMMS_READ_EBX_OFFSET \
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DIMM0_READ ; \
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DIMM1_READ ; \
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DIMM2_READ ; \
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DIMM3_READ ; \
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DIMM4_READ ; \
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DIMM5_READ ; \
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DIMM1_READ ;
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// DIMM2_READ ; \
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// DIMM3_READ ; \
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// DIMM4_READ ; \
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// DIMM5_READ ; \
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#define DIMMS_READ(offset) \
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movl $offset, %ebx ; \
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DIMMS_READ_EBX_OFFSET
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// movl $offset, %ebx ; \
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// DIMMS_READ_EBX_OFFSET
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#define RAM_COMMAND_NONE 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x4
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#define RAM_COMMAND_NONE $0x0
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#define RAM_COMMAND_NOP $0x40
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#define RAM_COMMAND_PRECHARGE $0x80
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#define RAM_COMMAND_MRS $0xc0
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#define RAM_COMMAND_CBR $0x100
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#define SET_RAM_COMMAND(command) \
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movl $0x54, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x1F, %eax ; \
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orl $((command) << 5), %eax ; \
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movl %eax, %edx ; \
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movl $0x54, %eax ; \
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PCI_WRITE_CONFIG_BYTE
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// movl $0x54, %eax ; \
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// PCI_READ_CONFIG_WORD ; \
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// andl $~0x1c0, %eax ; \
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// orl command, %eax ; \
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// movl %eax, %ecx ; \
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// movl $0x54, %eax ; \
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// PCI_WRITE_CONFIG_WORD
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#define COMPUTE_CAS_MODE \
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movl $0x54, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x10, %eax ; \
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xorl $0x10, %eax ; \
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shll $2, %eax ; \
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orl $0x2a, %eax ; \
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// movl $0x54, %eax ; \
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// PCI_READ_CONFIG_WORD ; \
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// andl $0x10, %eax ; \
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// xorl $0x10, %eax ; \
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// shll $2, %eax ; \
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// orl $0x2a, %eax ; \
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#define SET_RAM_MODE_REGISTER \
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SET_RAM_COMMAND(RAM_COMMAND_MRS) ; \
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COMPUTE_CAS_MODE ; \
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shll $3, %eax ; \
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movl %eax, %ebx ; \
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DIMMS_READ_EBX_OFFSET
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// SET_RAM_COMMAND(RAM_COMMAND_MRS) ; \
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// COMPUTE_CAS_MODE ; \
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// shll $3, %eax ; \
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// movl %eax, %ebx ; \
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// DIMMS_READ_EBX_OFFSET
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#define ASSERT_RAM_COMMAND() DIMMS_READ(RAM_READ)
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#define ASSERT_MRS_RAM_COMMAND(mode) DIMMS_READ(mode)
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#define ENABLE_REFRESH() CALL_LABEL(spd_enable_refresh)
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/* Default values for config registers */
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/* #define SET_NBXCFG \
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CS_WRITE_LONG(0x50, 0xff00a00c) */
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#define SET_DRAMC \
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CS_WRITE_BYTE(0x67, 0xB0) ;\
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CS_WRITE_BYTE(0x68, 0xF0)
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// CS_WRITE_BYTE(0x67, 0x83) ;\
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// CS_WRITE_BYTE(0x68, 0x30)
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/* PAM - Programmable Attribute Map Registers */
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/* Ideally we want to enable all of these as DRAM and teach
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* linux it is o.k. to use them...
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*/
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#define SET_PAM \
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CS_WRITE_BYTE(0x59, 0x00) ; \
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CS_WRITE_BYTE(0x5a, 0x00) ; \
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CS_WRITE_BYTE(0x5b, 0x00) ; \
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CS_WRITE_BYTE(0x5c, 0x00) ; \
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CS_WRITE_BYTE(0x5d, 0x00) ; \
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CS_WRITE_BYTE(0x5e, 0x00) ; \
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CS_WRITE_BYTE(0x5f, 0x00)
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// CS_WRITE_BYTE(0x59, 0x00) ; \
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// CS_WRITE_BYTE(0x5a, 0x00) ; \
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// CS_WRITE_BYTE(0x5b, 0x00) ; \
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// CS_WRITE_BYTE(0x5c, 0x00) ; \
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// CS_WRITE_BYTE(0x5d, 0x00) ; \
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// CS_WRITE_BYTE(0x5e, 0x00) ; \
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// CS_WRITE_BYTE(0x5f, 0x00)
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#define SET_DRB \
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/* DRB - DRAM Row Boundary Registers */ \
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CS_WRITE_BYTE(0x60, DRB) ; \
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CS_WRITE_BYTE(0x61, DRB) ; \
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CS_WRITE_BYTE(0x62, DRB) ; \
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CS_WRITE_BYTE(0x63, DRB) ; \
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CS_WRITE_BYTE(0x64, DRB) ; \
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CS_WRITE_BYTE(0x65, DRB) ; \
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// CS_WRITE_BYTE(0x60, DRB0) ; \
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// CS_WRITE_BYTE(0x61, DRB1) ; \
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// CS_WRITE_BYTE(0x62, DRB2) ; \
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// CS_WRITE_BYTE(0x63, DRB3) ; \
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// CS_WRITE_BYTE(0x64, DRB4) ; \
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// CS_WRITE_BYTE(0x65, DRB5) ; \
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#define SET_FDHC \
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CS_WRITE_BYTE(0x57, 0x01)
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/* #define SET_RPS \
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CS_WRITE_WORD(0x74, 0x0000)*/
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//CS_WRITE_BYTE(0x57, 0x01)
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#define SET_SDRAMC \
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CS_WRITE_BYTE(0x54, 0x00)
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//CS_WRITE_BYTE(0x54, 0x02)
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/* #define SET_PGPOL \
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CS_WRITE_WORD(0x78, 0xff00)*/
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#define SET_DRAMEC \
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//CS_WRITE_BYTE(0x56, 0x50)
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#define SET_DRAMT \
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//CS_WRITE_BYTE(0x58, 0x2b)
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#define SET_CACHE_CONTROL \
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//CS_WRITE_BYTE(0x52, 0x41)
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#define SET_SMRAMC \
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//CS_WRITE_BYTE(0x72, 0x02)
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/* PMCR - Power Management Control Register
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Enable normal refresh operation and
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the gated clock */
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#define SET_PMCR \
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CS_WRITE_BYTE(0x79, 0x10)
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//CS_WRITE_BYTE(0x79, 0x00)
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/* ********* AS OF NOW, ONLY ERIC'S CODE WORKS ************* */
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ram_set_registers:
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/* SET_NBXCFG */
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/* This directly from Eric's code */
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/* Disable and invalidate the cache */
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invd
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mov %cr0, %eax
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or $0x60000000, %eax
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mov %eax, %cr0
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CS_WRITE_BYTE(0x5E, 0x55)
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CS_WRITE_BYTE(0x5F, 0x22)
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/* Read it and make sure the write was successful */
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mov $0x5E, %eax
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PCI_READ_CONFIG_BYTE
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cmp $0x55, %al
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jne north_err
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mov $0x5F, %eax
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PCI_READ_CONFIG_BYTE
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cmp $0x22, %al
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jne north_err
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north_ok:
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CS_WRITE_BYTE(0x57,0x00) // DRAM Control Register
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CS_WRITE_WORD(0x04, 0x0006) // PCI Command Register
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CS_WRITE_BYTE(0x0D,0x20) // Master Latency Timer Register
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CS_WRITE_BYTE(0x4F,0x00) // Arbitration Control Register
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CS_WRITE_BYTE(0x50,0x00) // PCI Control Register
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CS_WRITE_BYTE(0x52,0x00) // Cache Control Register
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CS_WRITE_BYTE(0x56,0x50) // DRAM Extended Control Register
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CS_WRITE_BYTE(0x58,0x2b) // DRAM Timing Register
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// 7 = readable, writeable, cacheable
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/* CS_WRITE_BYTE(0x59,0x50) // PAM0 Register
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CS_WRITE_BYTE(0x5A,0x55) // PAM1 Register
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CS_WRITE_BYTE(0x5B,0x00) // PAM2 Register
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CS_WRITE_BYTE(0x5C,0x00) // PAM3 Register
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CS_WRITE_BYTE(0x5D,0x30) // PAM4 Register
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CS_WRITE_BYTE(0x5E,0x54) // PAM5 Register
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CS_WRITE_BYTE(0x5F,0x55) // PAM6 Register */
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// Recognize only 64 MBs of RAM for now!!!!!!!!!!!!!!
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CS_WRITE_BYTE(0x60,0x10) // DRB0 Register
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CS_WRITE_BYTE(0x61,0x10) // DRB1 Register
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CS_WRITE_BYTE(0x62,0x10) // DRB2 Register
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CS_WRITE_BYTE(0x63,0x10) // DRB3 Register
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CS_WRITE_BYTE(0x64,0x10) // DRB4 Register
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CS_WRITE_BYTE(0x65,0x10) // DRB5 Register
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// CS_WRITE_BYTE(0x67,0xf0) DRTH DRAM Row Type High
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CS_WRITE_BYTE(0x68,0xf0) // DRTH DRAM Row Type Low
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CS_WRITE_BYTE(0x72,0x02) // SMRAM Control Rgister
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CS_WRITE_BYTE(0x90,0x00) // Error Command Register
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// HERE BEGINS THE DRAM SETUP
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CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
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mov $0x1000, %ecx
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loop .
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CALLSP(dumpnorth)
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mov 0x00, %eax // dummy read to issue SDRAM NOP
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/* delay 200 us*/
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mov $0x1000, %ecx
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loop .
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#if 0
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CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
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mov $0x10000, %ecx
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loop .
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CONSOLE_DEBUG_TX_STRING($before_zero_nop)
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mov 0x0000000, %eax // dummy read to issue SDRAM NOP
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CONSOLE_DEBUG_TX_STRING($after_zero_nop)
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/* delay 200 us*/
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mov $0x1000, %ecx
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loop .
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#endif
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/* SDRAM Precharge all */
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CS_WRITE_WORD(0x54,0x0082)
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mov $0x1000, %ecx
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loop .
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CONSOLE_DEBUG_TX_STRING($after_fifty_four)
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mov 0x00, %eax // dummy read to make precharge happen
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mov $0x1000, %ecx
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loop .
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CONSOLE_DEBUG_TX_STRING($after_zero)
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/* SDRAM CBR Refresh */
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CS_WRITE_WORD(0x54,0x0102)
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mov $8, %ebx // cycle 8 times
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9:
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mov 0x00, %eax // dummy read
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mov $10, %ecx // brief delay
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loop .
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dec %ebx
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jnz 9b
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/* SDRAM MRS command mode */
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CS_WRITE_WORD(0x54,0x00C2)
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/* kind of weird since the mode is actually the address bits [11..0].
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* the address read is 1d0, which means burst length 4,
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* wrap type interleaved, CAS latency 3 */
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mov 0x1d0, %eax
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/* note if we ever add more banks of memory we'll have to add more lines
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* like the last one */
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// WE NEED THE CONFIGURE FOR THE OTHER SIDE TOO - Ron helped me with this, Bharath!
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// mov 0x40001d0, %eax
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/* Put SDRAM in normal mode and enable refresh */
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CS_WRITE_WORD(0x54,0x0002)
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CONSOLE_DEBUG_TX_STRING($firsttime)
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// HERE ENDS DRAM SETUP
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//******************** THIS DOESN'T WORK - Chipset goes nuts, crashes ********************** /
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#if 0
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// HERE BEGINS THE DRAM SETUP
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CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
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mov $0x1000, %ecx
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loop .
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CALLSP(dumpnorth)
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CONSOLE_DEBUG_TX_STRING($before_zero_nop)
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mov 0x00, %eax // dummy read to issue SDRAM NOP
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/* delay 200 us*/
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mov $0x1000, %ecx
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loop .
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#if 0
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CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
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mov $0x10000, %ecx
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loop .
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CONSOLE_DEBUG_TX_STRING($before_zero_nop)
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mov 0x0000000, %eax // dummy read to issue SDRAM NOP
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CONSOLE_DEBUG_TX_STRING($after_zero_nop)
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/* delay 200 us*/
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mov $0x1000, %ecx
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loop .
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#endif
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/* SDRAM Precharge all */
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CS_WRITE_WORD(0x54,0x0082)
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mov $0x1000, %ecx
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loop .
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CONSOLE_DEBUG_TX_STRING($after_fifty_four)
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mov 0x00, %eax // dummy read to make precharge happen
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mov $0x1000, %ecx
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loop .
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||||
CONSOLE_DEBUG_TX_STRING($after_zero)
|
||||
|
||||
/* SDRAM CBR Refresh */
|
||||
CS_WRITE_WORD(0x54,0x0102)
|
||||
mov $8, %ebx // cycle 8 times
|
||||
9:
|
||||
mov 0x00, %eax // dummy read
|
||||
mov $10, %ecx // brief delay
|
||||
loop .
|
||||
dec %ebx
|
||||
jnz 9b
|
||||
|
||||
/* SDRAM MRS command mode */
|
||||
CS_WRITE_WORD(0x54,0x00C2)
|
||||
|
||||
/* kind of weird since the mode is actually the address bits [11..0].
|
||||
* the address read is 1d0, which means burst length 4,
|
||||
* wrap type interleaved, CAS latency 3 */
|
||||
|
||||
mov 0x1d0, %eax
|
||||
/* note if we ever add more banks of memory we'll have to add more lines
|
||||
* like the last one */
|
||||
|
||||
// WE NEED THE CONFIGURE FOR THE OTHER SIDE TOO - Ron helped me with this, Bharath!
|
||||
// mov 0x40001d0, %eax
|
||||
|
||||
|
||||
/* Put SDRAM in normal mode and enable refresh */
|
||||
CS_WRITE_WORD(0x54,0x0002)
|
||||
CONSOLE_DEBUG_TX_STRING($secondtime)
|
||||
// HERE ENDS DRAM SETUP
|
||||
#endif
|
||||
|
||||
|
||||
// ENABLE REFRESH
|
||||
CS_WRITE_BYTE(0x57,0x01)
|
||||
|
||||
/* enable the cache */
|
||||
CS_WRITE_BYTE(0x52,0x42) // force invalidate
|
||||
cld
|
||||
mov $0, %esi
|
||||
mov $0x10000, %ecx // 246kB cache / 4 = 0x10000
|
||||
rep
|
||||
lodsl
|
||||
|
||||
CS_WRITE_BYTE(0x52,0x41) // cache enable, normal mode
|
||||
mov %cr0, %eax
|
||||
and $0x9ffffff, %eax // cache disable bits off
|
||||
mov %eax, %cr0
|
||||
|
||||
/* ****************************** */
|
||||
#if 0
|
||||
SET_SDRAMC
|
||||
SET_DRAMT
|
||||
SET_DRAMC
|
||||
SET_DRAMEC
|
||||
/* SET_CACHE_CONTROL */
|
||||
SET_FDHC
|
||||
SET_PAM
|
||||
SET_DRB
|
||||
SET_FDHC
|
||||
/* SET_RPS */
|
||||
SET_SDRAMC
|
||||
/* SET_PGPOL */
|
||||
SET_PMCR
|
||||
/* SET_SMRAMC */
|
||||
#endif
|
||||
RET_LABEL(ram_set_registers)
|
||||
|
||||
|
||||
|
|
@ -178,6 +418,7 @@ enable_smbus:
|
|||
CS_WRITE_WORD(PM_FUNCTION + 0x4, 1) /* iospace enable */
|
||||
RET_LABEL(enable_smbus)
|
||||
|
||||
|
||||
/*
|
||||
* Routine: setup_smbus
|
||||
* Arguments: none
|
||||
|
|
@ -195,6 +436,7 @@ setup_smbus:
|
|||
#define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1)
|
||||
#define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2)
|
||||
#define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3)
|
||||
#define SMBUS_MEM_DEVICE_LAST SMBUS_MEM_DEVICE_0
|
||||
|
||||
|
||||
smbus_wait_until_ready:
|
||||
|
|
@ -258,7 +500,7 @@ smbus_read_byte:
|
|||
RETSP
|
||||
|
||||
configure_rps_pgpol_drb:
|
||||
|
||||
#if 0
|
||||
/* %bl is the row index */
|
||||
xorl %ebx, %ebx
|
||||
|
||||
|
|
@ -284,7 +526,7 @@ next_row:
|
|||
|
||||
testb $2, %al
|
||||
jnz two_rows
|
||||
testb $1, %bl
|
||||
testb $2, %bl
|
||||
/* this used to be jnz but seems it should be jz */
|
||||
jz ready_for_next_row
|
||||
|
||||
|
|
@ -320,7 +562,7 @@ two_rows:
|
|||
CALLSP(smbus_read_byte)
|
||||
shr $16, %ebx
|
||||
|
||||
shr $1, %al
|
||||
/* shr $1, %al */
|
||||
xorb %ah, %ah
|
||||
add %ax, %cx
|
||||
movzx %cx, %edx
|
||||
|
|
@ -347,18 +589,19 @@ ready_for_next_row:
|
|||
|
||||
/* Now to finally write the RPS and PGPOL registers */
|
||||
|
||||
movzx %si, %ecx
|
||||
/* movzx %si, %ecx
|
||||
movl $0x74, %eax
|
||||
PCI_WRITE_CONFIG_WORD
|
||||
|
||||
mov %di, %cx
|
||||
movzx %ch, %edx
|
||||
movl $0x79, %eax
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
|
||||
PCI_WRITE_CONFIG_BYTE */
|
||||
#endif
|
||||
RET_LABEL(configure_rps_pgpol_drb)
|
||||
|
||||
configure_sdramc:
|
||||
#if 0
|
||||
movl $((18 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
||||
0: CALLSP(smbus_read_byte)
|
||||
jnz 1f
|
||||
|
|
@ -374,9 +617,11 @@ configure_sdramc:
|
|||
cmpb $SMBUS_MEM_DEVICE_3, %bl
|
||||
jbe 0b
|
||||
2:
|
||||
#endif
|
||||
RET_LABEL(configure_sdramc)
|
||||
|
||||
spd_set_dramc:
|
||||
#if 0
|
||||
movl $((21 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
||||
1: CALLSP(smbus_read_byte)
|
||||
jnz 2f
|
||||
|
|
@ -396,6 +641,7 @@ spd_set_dramc_out:
|
|||
1: movl %eax, %edx
|
||||
movl $0x57, %eax
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
#endif
|
||||
RET_LABEL(spd_set_dramc)
|
||||
|
||||
|
||||
|
|
@ -419,6 +665,7 @@ refresh_rates:
|
|||
.byte 0x04 /* Extended(8x) 125 us -> 124.8 us */
|
||||
|
||||
spd_enable_refresh:
|
||||
#if 0
|
||||
/* Find the first dimm and assume the rest are the same */
|
||||
/* Load the smbus device and port int %ebx */
|
||||
movl $((12 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
||||
|
|
@ -447,9 +694,11 @@ spd_enable_refresh_out:
|
|||
movb %al, %dl
|
||||
movl $0x57, %eax
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
#endif
|
||||
RET_LABEL(spd_enable_refresh)
|
||||
|
||||
spd_set_nbxcfg:
|
||||
#if 0
|
||||
/* say all dimms have no ECC support */
|
||||
movl $0xFF, %esi
|
||||
/* Index into %esi of bit to set */
|
||||
|
|
@ -487,19 +736,40 @@ spd_set_nbxcfg:
|
|||
|
||||
movl $((126 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
||||
CALLSP(smbus_read_byte)
|
||||
|
||||
#endif
|
||||
RET_LABEL(spd_set_nbxcfg)
|
||||
|
||||
ram_set_spd_registers:
|
||||
CALL_LABEL(enable_smbus)
|
||||
CALL_LABEL(setup_smbus)
|
||||
CALL_LABEL(configure_sdramc)
|
||||
CALL_LABEL(configure_rps_pgpol_drb)
|
||||
CALL_LABEL(spd_set_dramc)
|
||||
CALL_LABEL(spd_set_nbxcfg)
|
||||
// CALL_LABEL(enable_smbus)
|
||||
enable_smbus_done:
|
||||
// CONSOLE_DEBUG_TX_STRING($after_enable_smbus)
|
||||
// CALLSP(dumpnorth)
|
||||
|
||||
// CALL_LABEL(setup_smbus)
|
||||
setup_smbus_done:
|
||||
// CONSOLE_DEBUG_TX_STRING($after_setup_smbus)
|
||||
// CALLSP(dumpnorth)
|
||||
|
||||
// CALL_LABEL(configure_sdramc)
|
||||
configure_sdramc_done:
|
||||
// CONSOLE_DEBUG_TX_STRING($after_configure_sdramc)
|
||||
// CALLSP(dumpnorth)
|
||||
|
||||
// CALL_LABEL(configure_rps_pgpol_drb)
|
||||
configure_rps_pgpol_drb_done:
|
||||
// CONSOLE_DEBUG_TX_STRING($after_configure_drb)
|
||||
// CALLSP(dumpnorth)
|
||||
|
||||
// CALL_LABEL(spd_set_dramc)
|
||||
spd_set_dramc_done:
|
||||
// CALL_LABEL(spd_set_nbxcfg)
|
||||
spd_set_nbxcfg_done:
|
||||
RET_LABEL(ram_set_spd_registers)
|
||||
|
||||
/* stuff for Eric's code */
|
||||
north_err:
|
||||
CONSOLE_DEBUG_TX_STRING($north_bridge_error)
|
||||
jmp north_ok
|
||||
|
||||
/* things that are not used */
|
||||
#define FIRST_NORMAL_REFERENCE()
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue