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smartcore p5 support.

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This commit is contained in:
Ronald G. Minnich 2001-12-18 23:53:52 +00:00
parent 402332c59c
commit 523a37fb8f
2 changed files with 373 additions and 94 deletions
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21
src/mainboard/digitallogic/smartcore-p5/config.example
View file

@ -1,20 +1,29 @@
# Sample config file for digital logic smartcore-p5 # Sample config file for Intel 430TX chipset on the Smartcore P5
# This will make a target directory of ./smartcore-p5
target smartcore-p5 target smartcore-p5
# ASUS CUA main board
mainboard digitallogic/smartcore-p5 mainboard digitallogic/smartcore-p5
# option HAVE_PIRQ_TABLE=1
# Enable Serial Console for debugging # Enable Serial Console for debugging
option SERIAL_CONSOLE=1 option SERIAL_CONSOLE=1
option NO_KEYBOARD option NO_KEYBOARD
option INBUF_COPY option INBUF_COPY
option DEFAULT_CONSOLE_LOGLEVEL=9 option DEFAULT_CONSOLE_LOGLEVEL=9
option DEBUG option DEBUG
option USE_GENERIC_ROM=1 option USE_GENERIC_ROM=1
# Path to your kernel (vmlinux) # MEMORY TESTING USING MEMTEST
linux ~/src/bios/linux-2.4.7-sis option USE_ELF_BOOT=1
# *****************MODIFIED BY BHARATH********************
# Path to your kernel (vmlinux)
linux /users/bxmx/kernels/vmlinux-2.4.14
# Kernel command line parameters # Kernel command line parameters
commandline root=/dev/hda6 console=ttyS0,115200 FS_MODE=ro hda=flash hdb=flash # *******************MODIFIED BY BHARATH ****************
commandline root=/dev/hdc2 console=ttyS0,115200 floppy=nodma single
option RAMTEST

446
src/northbridge/intel/430tx/raminit.inc
View file

@ -1,5 +1,26 @@
jmp intel_430_out jmp intel_430_out
/* **** Bharath's debugging crap *********** */
after_enable_smbus: .string "After enable_smbus\r\n"
after_setup_smbus: .string "After setup_smbus\r\n"
after_configure_sdramc: .string "After configure_sdramc\r\n"
after_configure_drb: .string "After configure_drb\r\n"
before_pci_read: .string "Before PCI Read\r\n"
after_pci_read: .string "After PCI Read\r\n"
before_mem_read: .string "Before 0x0400 Read\r\n"
after_mem_read: .string "After 0x0400 Read\r\n"
north_bridge_error: .string "OOps, can't write to PAM registers properly\r\n"
after_zero: .string "After 0x00...\r\n"
before_zero_nop: .string "Before 0x0000000 nop...\r\n"
after_zero_nop: .string "After 0x0000000 nop...\r\n"
after_one_million: .string "After 0x0000000...\r\n"
after_fifty_four: .string "After 0x54...\r\n"
firsttime: .string "First DRAM setup done\r\n"
secondtime: .string "Second DRAM setup done\r\n"
/* **** End Bharath's debugging crap **** */
#define USE_SPD 1 #define USE_SPD 1
#define CS_WRITE_BYTE(addr, byte) \ #define CS_WRITE_BYTE(addr, byte) \
@ -18,7 +39,12 @@ jmp intel_430_out
PCI_WRITE_CONFIG_DWORD PCI_WRITE_CONFIG_DWORD
/* Default memory set to 0 */ /* Default memory set to 0 */
#define DRB 0x00 #define DRB0 0x10
#define DRB1 0x20
#define DRB2 0x20
#define DRB3 0x20
#define DRB4 0x20
#define DRB5 0x20
/* The DRB register for the first row */ /* The DRB register for the first row */
#define DRB_REG0 $0x60 #define DRB_REG0 $0x60
@ -32,19 +58,23 @@ jmp intel_430_out
xorl %eax, %eax xorl %eax, %eax
#define DIMM_BASE(n) \ #define DIMM_BASE(n) \
movl $(0x60 + ((n) -1)), %eax ; \ // CONSOLE_DEBUG_TX_STRING($before_pci_read) ; \
PCI_READ_CONFIG_BYTE ; \ // movl n, %eax ; \
andl $0xFF, %eax ; \ // PCI_READ_CONFIG_BYTE ; \
shll $22, %eax ; /* 4 MB granularity for the 430TX */ // CONSOLE_DEBUG_TX_STRING($after_pci_read) ; \
// andl $0xFF, %eax ; \
// shll $22, %eax ; /* 4 MB granularity for the 430TX */
#define DIMM_READ \ #define DIMM_READ \
addl %ebx, %eax ; \ // addl %ebx, %eax ; \
movl (%eax), %edx ; \ // CONSOLE_DEBUG_TX_STRING($before_mem_read) ; \
xorl $0xdff8, %eax ; \ // movl (%eax), %edx ;
movl (%eax), %edx // CONSOLE_DEBUG_TX_STRING($after_mem_read) ; \
// xorl $0xdff8, %eax ; \
// movl (%eax), %edx
#define DIMM0_READ DIMM0_BASE ; DIMM_READ #define DIMM0_READ DIMM0_BASE ; DIMM_READ
#define DIMM1_READ DIMM_BASE(1) ; DIMM_READ #define DIMM1_READ DIMM_BASE($0x60) ; DIMM_READ
#define DIMM2_READ DIMM_BASE(2) ; DIMM_READ #define DIMM2_READ DIMM_BASE(2) ; DIMM_READ
#define DIMM3_READ DIMM_BASE(3) ; DIMM_READ #define DIMM3_READ DIMM_BASE(3) ; DIMM_READ
#define DIMM4_READ DIMM_BASE(4) ; DIMM_READ #define DIMM4_READ DIMM_BASE(4) ; DIMM_READ
@ -52,110 +82,320 @@ jmp intel_430_out
#define DIMMS_READ_EBX_OFFSET \ #define DIMMS_READ_EBX_OFFSET \
DIMM0_READ ; \ DIMM0_READ ; \
DIMM1_READ ; \ DIMM1_READ ;
DIMM2_READ ; \ // DIMM2_READ ; \
DIMM3_READ ; \ // DIMM3_READ ; \
DIMM4_READ ; \ // DIMM4_READ ; \
DIMM5_READ ; \ // DIMM5_READ ; \
#define DIMMS_READ(offset) \ #define DIMMS_READ(offset) \
movl $offset, %ebx ; \ // movl $offset, %ebx ; \
DIMMS_READ_EBX_OFFSET // DIMMS_READ_EBX_OFFSET
#define RAM_COMMAND_NONE 0x0 #define RAM_COMMAND_NONE $0x0
#define RAM_COMMAND_NOP 0x1 #define RAM_COMMAND_NOP $0x40
#define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_PRECHARGE $0x80
#define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_MRS $0xc0
#define RAM_COMMAND_CBR 0x4 #define RAM_COMMAND_CBR $0x100
#define SET_RAM_COMMAND(command) \ #define SET_RAM_COMMAND(command) \
movl $0x54, %eax ; \ // movl $0x54, %eax ; \
PCI_READ_CONFIG_BYTE ; \ // PCI_READ_CONFIG_WORD ; \
andl $0x1F, %eax ; \ // andl $~0x1c0, %eax ; \
orl $((command) << 5), %eax ; \ // orl command, %eax ; \
movl %eax, %edx ; \ // movl %eax, %ecx ; \
movl $0x54, %eax ; \ // movl $0x54, %eax ; \
PCI_WRITE_CONFIG_BYTE // PCI_WRITE_CONFIG_WORD
#define COMPUTE_CAS_MODE \ #define COMPUTE_CAS_MODE \
movl $0x54, %eax ; \ // movl $0x54, %eax ; \
PCI_READ_CONFIG_BYTE ; \ // PCI_READ_CONFIG_WORD ; \
andl $0x10, %eax ; \ // andl $0x10, %eax ; \
xorl $0x10, %eax ; \ // xorl $0x10, %eax ; \
shll $2, %eax ; \ // shll $2, %eax ; \
orl $0x2a, %eax ; \ // orl $0x2a, %eax ; \
#define SET_RAM_MODE_REGISTER \ #define SET_RAM_MODE_REGISTER \
SET_RAM_COMMAND(RAM_COMMAND_MRS) ; \ // SET_RAM_COMMAND(RAM_COMMAND_MRS) ; \
COMPUTE_CAS_MODE ; \ // COMPUTE_CAS_MODE ; \
shll $3, %eax ; \ // shll $3, %eax ; \
movl %eax, %ebx ; \ // movl %eax, %ebx ; \
DIMMS_READ_EBX_OFFSET // DIMMS_READ_EBX_OFFSET
#define ASSERT_RAM_COMMAND() DIMMS_READ(RAM_READ) #define ASSERT_RAM_COMMAND() DIMMS_READ(RAM_READ)
#define ASSERT_MRS_RAM_COMMAND(mode) DIMMS_READ(mode) #define ASSERT_MRS_RAM_COMMAND(mode) DIMMS_READ(mode)
#define ENABLE_REFRESH() CALL_LABEL(spd_enable_refresh) #define ENABLE_REFRESH() CALL_LABEL(spd_enable_refresh)
/* Default values for config registers */ /* Default values for config registers */
/* #define SET_NBXCFG \
CS_WRITE_LONG(0x50, 0xff00a00c) */
#define SET_DRAMC \ #define SET_DRAMC \
CS_WRITE_BYTE(0x67, 0xB0) ;\ // CS_WRITE_BYTE(0x67, 0x83) ;\
CS_WRITE_BYTE(0x68, 0xF0) // CS_WRITE_BYTE(0x68, 0x30)
/* PAM - Programmable Attribute Map Registers */ /* PAM - Programmable Attribute Map Registers */
/* Ideally we want to enable all of these as DRAM and teach /* Ideally we want to enable all of these as DRAM and teach
* linux it is o.k. to use them... * linux it is o.k. to use them...
*/ */
#define SET_PAM \ #define SET_PAM \
CS_WRITE_BYTE(0x59, 0x00) ; \ // CS_WRITE_BYTE(0x59, 0x00) ; \
CS_WRITE_BYTE(0x5a, 0x00) ; \ // CS_WRITE_BYTE(0x5a, 0x00) ; \
CS_WRITE_BYTE(0x5b, 0x00) ; \ // CS_WRITE_BYTE(0x5b, 0x00) ; \
CS_WRITE_BYTE(0x5c, 0x00) ; \ // CS_WRITE_BYTE(0x5c, 0x00) ; \
CS_WRITE_BYTE(0x5d, 0x00) ; \ // CS_WRITE_BYTE(0x5d, 0x00) ; \
CS_WRITE_BYTE(0x5e, 0x00) ; \ // CS_WRITE_BYTE(0x5e, 0x00) ; \
CS_WRITE_BYTE(0x5f, 0x00) // CS_WRITE_BYTE(0x5f, 0x00)
#define SET_DRB \ #define SET_DRB \
/* DRB - DRAM Row Boundary Registers */ \ /* DRB - DRAM Row Boundary Registers */ \
CS_WRITE_BYTE(0x60, DRB) ; \ // CS_WRITE_BYTE(0x60, DRB0) ; \
CS_WRITE_BYTE(0x61, DRB) ; \ // CS_WRITE_BYTE(0x61, DRB1) ; \
CS_WRITE_BYTE(0x62, DRB) ; \ // CS_WRITE_BYTE(0x62, DRB2) ; \
CS_WRITE_BYTE(0x63, DRB) ; \ // CS_WRITE_BYTE(0x63, DRB3) ; \
CS_WRITE_BYTE(0x64, DRB) ; \ // CS_WRITE_BYTE(0x64, DRB4) ; \
CS_WRITE_BYTE(0x65, DRB) ; \ // CS_WRITE_BYTE(0x65, DRB5) ; \
#define SET_FDHC \ #define SET_FDHC \
CS_WRITE_BYTE(0x57, 0x01) //CS_WRITE_BYTE(0x57, 0x01)
/* #define SET_RPS \
CS_WRITE_WORD(0x74, 0x0000)*/
#define SET_SDRAMC \ #define SET_SDRAMC \
CS_WRITE_BYTE(0x54, 0x00) //CS_WRITE_BYTE(0x54, 0x02)
/* #define SET_PGPOL \ #define SET_DRAMEC \
CS_WRITE_WORD(0x78, 0xff00)*/ //CS_WRITE_BYTE(0x56, 0x50)
#define SET_DRAMT \
//CS_WRITE_BYTE(0x58, 0x2b)
#define SET_CACHE_CONTROL \
//CS_WRITE_BYTE(0x52, 0x41)
#define SET_SMRAMC \
//CS_WRITE_BYTE(0x72, 0x02)
/* PMCR - Power Management Control Register /* PMCR - Power Management Control Register
Enable normal refresh operation and Enable normal refresh operation and
the gated clock */ the gated clock */
#define SET_PMCR \ #define SET_PMCR \
CS_WRITE_BYTE(0x79, 0x10) //CS_WRITE_BYTE(0x79, 0x00)
/* ********* AS OF NOW, ONLY ERIC'S CODE WORKS ************* */
ram_set_registers: ram_set_registers:
/* SET_NBXCFG */ /* This directly from Eric's code */
/* Disable and invalidate the cache */
invd
mov %cr0, %eax
or $0x60000000, %eax
mov %eax, %cr0
CS_WRITE_BYTE(0x5E, 0x55)
CS_WRITE_BYTE(0x5F, 0x22)
/* Read it and make sure the write was successful */
mov $0x5E, %eax
PCI_READ_CONFIG_BYTE
cmp $0x55, %al
jne north_err
mov $0x5F, %eax
PCI_READ_CONFIG_BYTE
cmp $0x22, %al
jne north_err
north_ok:
CS_WRITE_BYTE(0x57,0x00) // DRAM Control Register
CS_WRITE_WORD(0x04, 0x0006) // PCI Command Register
CS_WRITE_BYTE(0x0D,0x20) // Master Latency Timer Register
CS_WRITE_BYTE(0x4F,0x00) // Arbitration Control Register
CS_WRITE_BYTE(0x50,0x00) // PCI Control Register
CS_WRITE_BYTE(0x52,0x00) // Cache Control Register
CS_WRITE_BYTE(0x56,0x50) // DRAM Extended Control Register
CS_WRITE_BYTE(0x58,0x2b) // DRAM Timing Register
// 7 = readable, writeable, cacheable
/* CS_WRITE_BYTE(0x59,0x50) // PAM0 Register
CS_WRITE_BYTE(0x5A,0x55) // PAM1 Register
CS_WRITE_BYTE(0x5B,0x00) // PAM2 Register
CS_WRITE_BYTE(0x5C,0x00) // PAM3 Register
CS_WRITE_BYTE(0x5D,0x30) // PAM4 Register
CS_WRITE_BYTE(0x5E,0x54) // PAM5 Register
CS_WRITE_BYTE(0x5F,0x55) // PAM6 Register */
// Recognize only 64 MBs of RAM for now!!!!!!!!!!!!!!
CS_WRITE_BYTE(0x60,0x10) // DRB0 Register
CS_WRITE_BYTE(0x61,0x10) // DRB1 Register
CS_WRITE_BYTE(0x62,0x10) // DRB2 Register
CS_WRITE_BYTE(0x63,0x10) // DRB3 Register
CS_WRITE_BYTE(0x64,0x10) // DRB4 Register
CS_WRITE_BYTE(0x65,0x10) // DRB5 Register
// CS_WRITE_BYTE(0x67,0xf0) DRTH DRAM Row Type High
CS_WRITE_BYTE(0x68,0xf0) // DRTH DRAM Row Type Low
CS_WRITE_BYTE(0x72,0x02) // SMRAM Control Rgister
CS_WRITE_BYTE(0x90,0x00) // Error Command Register
// HERE BEGINS THE DRAM SETUP
CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
mov $0x1000, %ecx
loop .
CALLSP(dumpnorth)
mov 0x00, %eax // dummy read to issue SDRAM NOP
/* delay 200 us*/
mov $0x1000, %ecx
loop .
#if 0
CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
mov $0x10000, %ecx
loop .
CONSOLE_DEBUG_TX_STRING($before_zero_nop)
mov 0x0000000, %eax // dummy read to issue SDRAM NOP
CONSOLE_DEBUG_TX_STRING($after_zero_nop)
/* delay 200 us*/
mov $0x1000, %ecx
loop .
#endif
/* SDRAM Precharge all */
CS_WRITE_WORD(0x54,0x0082)
mov $0x1000, %ecx
loop .
CONSOLE_DEBUG_TX_STRING($after_fifty_four)
mov 0x00, %eax // dummy read to make precharge happen
mov $0x1000, %ecx
loop .
CONSOLE_DEBUG_TX_STRING($after_zero)
/* SDRAM CBR Refresh */
CS_WRITE_WORD(0x54,0x0102)
mov $8, %ebx // cycle 8 times
9:
mov 0x00, %eax // dummy read
mov $10, %ecx // brief delay
loop .
dec %ebx
jnz 9b
/* SDRAM MRS command mode */
CS_WRITE_WORD(0x54,0x00C2)
/* kind of weird since the mode is actually the address bits [11..0].
* the address read is 1d0, which means burst length 4,
* wrap type interleaved, CAS latency 3 */
mov 0x1d0, %eax
/* note if we ever add more banks of memory we'll have to add more lines
* like the last one */
// WE NEED THE CONFIGURE FOR THE OTHER SIDE TOO - Ron helped me with this, Bharath!
// mov 0x40001d0, %eax
/* Put SDRAM in normal mode and enable refresh */
CS_WRITE_WORD(0x54,0x0002)
CONSOLE_DEBUG_TX_STRING($firsttime)
// HERE ENDS DRAM SETUP
//******************** THIS DOESN'T WORK - Chipset goes nuts, crashes ********************** /
#if 0
// HERE BEGINS THE DRAM SETUP
CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
mov $0x1000, %ecx
loop .
CALLSP(dumpnorth)
CONSOLE_DEBUG_TX_STRING($before_zero_nop)
mov 0x00, %eax // dummy read to issue SDRAM NOP
/* delay 200 us*/
mov $0x1000, %ecx
loop .
#if 0
CS_WRITE_WORD(0x54, 0x0042) // SDRAM Control Register
mov $0x10000, %ecx
loop .
CONSOLE_DEBUG_TX_STRING($before_zero_nop)
mov 0x0000000, %eax // dummy read to issue SDRAM NOP
CONSOLE_DEBUG_TX_STRING($after_zero_nop)
/* delay 200 us*/
mov $0x1000, %ecx
loop .
#endif
/* SDRAM Precharge all */
CS_WRITE_WORD(0x54,0x0082)
mov $0x1000, %ecx
loop .
CONSOLE_DEBUG_TX_STRING($after_fifty_four)
mov 0x00, %eax // dummy read to make precharge happen
mov $0x1000, %ecx
loop .
CONSOLE_DEBUG_TX_STRING($after_zero)
/* SDRAM CBR Refresh */
CS_WRITE_WORD(0x54,0x0102)
mov $8, %ebx // cycle 8 times
9:
mov 0x00, %eax // dummy read
mov $10, %ecx // brief delay
loop .
dec %ebx
jnz 9b
/* SDRAM MRS command mode */
CS_WRITE_WORD(0x54,0x00C2)
/* kind of weird since the mode is actually the address bits [11..0].
* the address read is 1d0, which means burst length 4,
* wrap type interleaved, CAS latency 3 */
mov 0x1d0, %eax
/* note if we ever add more banks of memory we'll have to add more lines
* like the last one */
// WE NEED THE CONFIGURE FOR THE OTHER SIDE TOO - Ron helped me with this, Bharath!
// mov 0x40001d0, %eax
/* Put SDRAM in normal mode and enable refresh */
CS_WRITE_WORD(0x54,0x0002)
CONSOLE_DEBUG_TX_STRING($secondtime)
// HERE ENDS DRAM SETUP
#endif
// ENABLE REFRESH
CS_WRITE_BYTE(0x57,0x01)
/* enable the cache */
CS_WRITE_BYTE(0x52,0x42) // force invalidate
cld
mov $0, %esi
mov $0x10000, %ecx // 246kB cache / 4 = 0x10000
rep
lodsl
CS_WRITE_BYTE(0x52,0x41) // cache enable, normal mode
mov %cr0, %eax
and $0x9ffffff, %eax // cache disable bits off
mov %eax, %cr0
/* ****************************** */
#if 0
SET_SDRAMC
SET_DRAMT
SET_DRAMC SET_DRAMC
SET_DRAMEC
/* SET_CACHE_CONTROL */
SET_FDHC
SET_PAM SET_PAM
SET_DRB SET_DRB
SET_FDHC SET_PMCR
/* SET_RPS */ /* SET_SMRAMC */
SET_SDRAMC #endif
/* SET_PGPOL */
SET_PMCR
RET_LABEL(ram_set_registers) RET_LABEL(ram_set_registers)
@ -178,6 +418,7 @@ enable_smbus:
CS_WRITE_WORD(PM_FUNCTION + 0x4, 1) /* iospace enable */ CS_WRITE_WORD(PM_FUNCTION + 0x4, 1) /* iospace enable */
RET_LABEL(enable_smbus) RET_LABEL(enable_smbus)
/* /*
* Routine: setup_smbus * Routine: setup_smbus
* Arguments: none * Arguments: none
@ -195,6 +436,7 @@ setup_smbus:
#define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1) #define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1)
#define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2) #define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2)
#define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3) #define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3)
#define SMBUS_MEM_DEVICE_LAST SMBUS_MEM_DEVICE_0
smbus_wait_until_ready: smbus_wait_until_ready:
@ -258,7 +500,7 @@ smbus_read_byte:
RETSP RETSP
configure_rps_pgpol_drb: configure_rps_pgpol_drb:
#if 0
/* %bl is the row index */ /* %bl is the row index */
xorl %ebx, %ebx xorl %ebx, %ebx
@ -284,7 +526,7 @@ next_row:
testb $2, %al testb $2, %al
jnz two_rows jnz two_rows
testb $1, %bl testb $2, %bl
/* this used to be jnz but seems it should be jz */ /* this used to be jnz but seems it should be jz */
jz ready_for_next_row jz ready_for_next_row
@ -320,7 +562,7 @@ two_rows:
CALLSP(smbus_read_byte) CALLSP(smbus_read_byte)
shr $16, %ebx shr $16, %ebx
shr $1, %al /* shr $1, %al */
xorb %ah, %ah xorb %ah, %ah
add %ax, %cx add %ax, %cx
movzx %cx, %edx movzx %cx, %edx
@ -343,22 +585,23 @@ ready_for_next_row:
1: 1:
inc %bl inc %bl
cmp MAX_ROWS, %bl cmp MAX_ROWS, %bl
jb next_row jb next_row
/* Now to finally write the RPS and PGPOL registers */ /* Now to finally write the RPS and PGPOL registers */
movzx %si, %ecx /* movzx %si, %ecx
movl $0x74, %eax movl $0x74, %eax
PCI_WRITE_CONFIG_WORD PCI_WRITE_CONFIG_WORD
mov %di, %cx mov %di, %cx
movzx %ch, %edx movzx %ch, %edx
movl $0x79, %eax movl $0x79, %eax
PCI_WRITE_CONFIG_BYTE PCI_WRITE_CONFIG_BYTE */
#endif
RET_LABEL(configure_rps_pgpol_drb) RET_LABEL(configure_rps_pgpol_drb)
configure_sdramc: configure_sdramc:
#if 0
movl $((18 << 8) | SMBUS_MEM_DEVICE_0), %ebx movl $((18 << 8) | SMBUS_MEM_DEVICE_0), %ebx
0: CALLSP(smbus_read_byte) 0: CALLSP(smbus_read_byte)
jnz 1f jnz 1f
@ -374,9 +617,11 @@ configure_sdramc:
cmpb $SMBUS_MEM_DEVICE_3, %bl cmpb $SMBUS_MEM_DEVICE_3, %bl
jbe 0b jbe 0b
2: 2:
#endif
RET_LABEL(configure_sdramc) RET_LABEL(configure_sdramc)
spd_set_dramc: spd_set_dramc:
#if 0
movl $((21 << 8) | SMBUS_MEM_DEVICE_0), %ebx movl $((21 << 8) | SMBUS_MEM_DEVICE_0), %ebx
1: CALLSP(smbus_read_byte) 1: CALLSP(smbus_read_byte)
jnz 2f jnz 2f
@ -396,6 +641,7 @@ spd_set_dramc_out:
1: movl %eax, %edx 1: movl %eax, %edx
movl $0x57, %eax movl $0x57, %eax
PCI_WRITE_CONFIG_BYTE PCI_WRITE_CONFIG_BYTE
#endif
RET_LABEL(spd_set_dramc) RET_LABEL(spd_set_dramc)
@ -419,6 +665,7 @@ refresh_rates:
.byte 0x04 /* Extended(8x) 125 us -> 124.8 us */ .byte 0x04 /* Extended(8x) 125 us -> 124.8 us */
spd_enable_refresh: spd_enable_refresh:
#if 0
/* Find the first dimm and assume the rest are the same */ /* Find the first dimm and assume the rest are the same */
/* Load the smbus device and port int %ebx */ /* Load the smbus device and port int %ebx */
movl $((12 << 8) | SMBUS_MEM_DEVICE_0), %ebx movl $((12 << 8) | SMBUS_MEM_DEVICE_0), %ebx
@ -447,9 +694,11 @@ spd_enable_refresh_out:
movb %al, %dl movb %al, %dl
movl $0x57, %eax movl $0x57, %eax
PCI_WRITE_CONFIG_BYTE PCI_WRITE_CONFIG_BYTE
#endif
RET_LABEL(spd_enable_refresh) RET_LABEL(spd_enable_refresh)
spd_set_nbxcfg: spd_set_nbxcfg:
#if 0
/* say all dimms have no ECC support */ /* say all dimms have no ECC support */
movl $0xFF, %esi movl $0xFF, %esi
/* Index into %esi of bit to set */ /* Index into %esi of bit to set */
@ -487,19 +736,40 @@ spd_set_nbxcfg:
movl $((126 << 8) | SMBUS_MEM_DEVICE_0), %ebx movl $((126 << 8) | SMBUS_MEM_DEVICE_0), %ebx
CALLSP(smbus_read_byte) CALLSP(smbus_read_byte)
#endif
RET_LABEL(spd_set_nbxcfg) RET_LABEL(spd_set_nbxcfg)
ram_set_spd_registers: ram_set_spd_registers:
CALL_LABEL(enable_smbus) // CALL_LABEL(enable_smbus)
CALL_LABEL(setup_smbus) enable_smbus_done:
CALL_LABEL(configure_sdramc) // CONSOLE_DEBUG_TX_STRING($after_enable_smbus)
CALL_LABEL(configure_rps_pgpol_drb) // CALLSP(dumpnorth)
CALL_LABEL(spd_set_dramc)
CALL_LABEL(spd_set_nbxcfg)
// CALL_LABEL(setup_smbus)
setup_smbus_done:
// CONSOLE_DEBUG_TX_STRING($after_setup_smbus)
// CALLSP(dumpnorth)
// CALL_LABEL(configure_sdramc)
configure_sdramc_done:
// CONSOLE_DEBUG_TX_STRING($after_configure_sdramc)
// CALLSP(dumpnorth)
// CALL_LABEL(configure_rps_pgpol_drb)
configure_rps_pgpol_drb_done:
// CONSOLE_DEBUG_TX_STRING($after_configure_drb)
// CALLSP(dumpnorth)
// CALL_LABEL(spd_set_dramc)
spd_set_dramc_done:
// CALL_LABEL(spd_set_nbxcfg)
spd_set_nbxcfg_done:
RET_LABEL(ram_set_spd_registers) RET_LABEL(ram_set_spd_registers)
/* stuff for Eric's code */
north_err:
CONSOLE_DEBUG_TX_STRING($north_bridge_error)
jmp north_ok
/* things that are not used */ /* things that are not used */
#define FIRST_NORMAL_REFERENCE() #define FIRST_NORMAL_REFERENCE()