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spd init
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161
src/northbridge/via/vt8601/raminitspd.inc
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161
src/northbridge/via/vt8601/raminitspd.inc
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/* SPD ram init */
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#define PM_DEVFN CONFIG_ADDR(0, 0x3c, 0)
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#define DRAM_CONFIG_PORT 0x5a
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#define REGISTERED_DRAM_REGISTER $0x69
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jmp raminitspd_end
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/* table of settings for initial registers */
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register_table:
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/* no memory clock enable -- overridden by SPD, we hope */
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.byte 0x78, 0x1
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/* safe initial values ... */
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.byte 0x68, 0x0
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.byte 0x6b, 0x0
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.byte 0x64, 0xe4 /* slowest ram setting. banks 0, 1 */
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.byte 0x65, 0xe4 /* banks 2, 3*/
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.byte 0x66, 0xe4 /* banks 4, 5 */
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.byte 0x6d, 0x5 /* 0x4 = 24 ma on ma[2:13],we#, 24ma on ras# */
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.byte 0x60, 0xff /* sdram in ALL banks. It's all we do. */
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/* set these to 0xee (128 MB VC SDRAM). In our working code we set to
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* 0x88, but VIA code recommends 0xee. Since we are SPD, in the end,
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* this initial setting will be over-ridden by SPD probe values.
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*/
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.byte 0x58, 0xee
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.byte 0x59, 0xee
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/* size the banks at max, they will be resized later. */
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.byte 0x5a, 0x20
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.byte 0x5b, 0x40
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.byte 0x5c, 0x60
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.byte 0x5d, 0x80
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.byte 0x5e, 0xa0
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.byte 0x5f, 0xc0
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.byte 0x56, 0xe0
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.byte 0x57, 0xff
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.byte 0x0 /* end of table */
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ram_set_registers:
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/* standard x86 loop on table until done code */
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/* assumes that: devfn is 0 (safe on anything we've seen) */
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/* which means addresses are a byte */
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/* address is first, then data */
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movl $register_table, %esi
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1:
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movb (%esi), %al
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testb %al, %al
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jz done_ram_set_registers
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inc %esi
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movb (%esi), %dl
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PCI_WRITE_CONFIG_BYTE
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inc %esi
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jmp 1b
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// I forget why we need this, but we do
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mov $0xa55a5aa5, %eax
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mov %eax, 0
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mov %eax, 0x4000000
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done_ram_set_registers: RET_LABEL(ram_set_registers)
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ram_set_spd_registers:
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CALL_LABEL(enable_smbus)
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CALL_LABEL(setup_smbus)
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CALL_LABEL(spd_set_drb)
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CALL_LABEL(spd_set_dramc)
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/* CALL_LABEL(spd_set_rps)*/
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/* CALL_LABEL(spd_set_sdramc)*/
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/* CALL_LABEL(spd_set_pgpol)*/
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/* CALL_LABEL(spd_set_nbxcfg)*/
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spd_set_rps_done:
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spd_set_pgpol_done:
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spd_set_nbxcfg_done:
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RET_LABEL(ram_set_spd_registers)
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#define SMBUS_IO_BASE 0xf00
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#define REGISTERED_DRAM $0x2
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#define NONREGISTERED_DRAM $0
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#define REGISTER_DRAM_REGISTER $0x69
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#define RAM_READ 0x0400
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#define DIMM0_BASE \
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xorl %eax, %eax
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#define DIMM_BASE(n) \
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movl $(0x5a + ((n) -1)), %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0xFF, %eax ; \
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shll $23, %eax ; \
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#define DIMM_READ \
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addl %ebx, %eax ; \
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movl (%eax), %edx ; \
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xorl $0xdff8, %eax ; \
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movl (%eax), %edx
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#define DIMM0_READ DIMM0_BASE ; DIMM_READ
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#define DIMM1_READ DIMM_BASE(1) ; DIMM_READ
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#define DIMM2_READ DIMM_BASE(2) ; DIMM_READ
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#define DIMM3_READ DIMM_BASE(3) ; DIMM_READ
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#define DIMM4_READ DIMM_BASE(4) ; DIMM_READ
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#define DIMM5_READ DIMM_BASE(5) ; DIMM_READ
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#define DIMM6_READ DIMM_BASE(6) ; DIMM_READ
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#define DIMM7_READ DIMM_BASE(7) ; DIMM_READ
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#define DIMMS_READ_EBX_OFFSET \
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DIMM0_READ ; \
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DIMM1_READ ; \
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DIMM2_READ ; \
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DIMM3_READ ; \
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DIMM4_READ ; \
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DIMM5_READ ; \
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DIMM6_READ ; \
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DIMM7_READ
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#define DIMMS_READ(offset) \
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movl $offset, %ebx ; \
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DIMMS_READ_EBX_OFFSET
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#define RAM_COMMAND_NONE 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x4
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#define SET_RAM_COMMAND(command) \
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movl $0x6c, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x14, %eax ; \
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orl $(command), %eax ; \
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movl %eax, %edx ; \
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movl $0x6c, %eax ; \
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PCI_WRITE_CONFIG_BYTE
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// fix me later. Have to have ram in slot 0, and we only test cas3 or 2
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#define COMPUTE_CAS_MODE \
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movl $0x64, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x20, %eax ; \
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xorl $0x20, %eax ; \
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shll $2, %eax ; \
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orl $0x2a, %eax ; \
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#define SET_RAM_MODE_REGISTER \
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SET_RAM_COMMAND(RAM_COMMAND_MRS) ; \
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COMPUTE_CAS_MODE ; \
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shll $3, %eax ; \
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movl %eax, %ebx ; \
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DIMMS_READ_EBX_OFFSET
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#define ASSERT_RAM_COMMAND() DIMMS_READ(RAM_READ)
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#define ASSERT_MRS_RAM_COMMAND(mode) DIMMS_READ(mode)
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#define USE_SPD 1
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#if ! USE_SPD
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#define ENABLE_REFRESH() CS_BIS_BYTE(0x57, 0x1)
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#else /* USE_SPD */
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#define ENABLE_REFRESH() CALL_LABEL(spd_enable_refresh)
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#endif
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spd_enable_refresh:
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// just set it for now.
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CS_WRITE($0x6A, $0x65)
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RET_LABEL(spd_enable_refresh)
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raminitspd_end:
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