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UPSTREAM: intel/amenia: Program EMMC dll setting

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EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.

BUG=None
BRANCH=None
TEST=None

Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Original-Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Original-Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15092
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351375
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Zhao, Lijian 2016-05-17 19:26:18 -07:00 • committed by chrome-bot
parent e6f5a9e886
commit 5165ee3b6a
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/intel/amenia/devicetree.cb
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@ -10,6 +10,11 @@ chip soc/intel/apollolake
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"
# EMMC TX DATA Delay 1#
# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF