Emulation/switch-coreboot
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Filling in core 2 support.

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This actually starts to get compile errors, instead of config errors. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@994 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-11-12 00:38:13 +00:00
parent 4ff32f25b7
commit 50403f09b2
4 changed files with 22 additions and 2 deletions
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2
Kconfig
View file

@ -114,6 +114,8 @@ config SOUTHBRIDGE_AMD_RS690
boolean boolean
config SOUTHBRIDGE_VIA_VT8237 config SOUTHBRIDGE_VIA_VT8237
boolean boolean
config SOUTHBRIDGE_INTEL_I82801GX
boolean
# Super I/Os: # Super I/Os:
config SUPERIO_WINBOND_W83627HF config SUPERIO_WINBOND_W83627HF

14
arch/x86/Kconfig
View file

@ -56,6 +56,14 @@ config CPU_AMD_K8
arch/x86/Makefile for more hints on possible values. arch/x86/Makefile for more hints on possible values.
It is usually set in mainboard/*/Kconfig. It is usually set in mainboard/*/Kconfig.
config CPU_INTEL_CORE2
boolean
help
CPU type. At the moment this option selects the reset vector and
Cache-as-RAM (CAR) implementation for a mainboard. See
arch/x86/Makefile for more hints on possible values.
It is usually set in mainboard/*/Kconfig.
config CPU_VIA_C7 config CPU_VIA_C7
boolean boolean
help help
@ -102,6 +110,7 @@ config K8_ALLOCATE_MMIO_RANGE
config LOGICAL_CPUS config LOGICAL_CPUS
hex hex
depends CPU_AMD_K8 depends CPU_AMD_K8
depends CPU_INTEL_CORE2
default 1 default 1
help help
How many logical CPUs there are. FIXME. How many logical CPUs there are. FIXME.
@ -157,7 +166,7 @@ config SMP
config IOAPIC config IOAPIC
boolean boolean
depends ARCH_X86 && CPU_AMD_K8 depends ARCH_X86 && CPU_AMD_K8 || CPU_INTEL_CORE2
default 0 default 0
help help
If you want to configure an IOAPIC, set this. If you want to configure an IOAPIC, set this.
@ -168,6 +177,7 @@ config CARBASE
default 0x80000 if CPU_AMD_GEODELX default 0x80000 if CPU_AMD_GEODELX
default 0xc8000 if CPU_AMD_K8 default 0xc8000 if CPU_AMD_K8
default 0xffef0000 if CPU_VIA_C7 default 0xffef0000 if CPU_VIA_C7
default 0xffef0000 if CPU_INTEL_CORE2
help help
This option sets the base address of the area used for CAR. This option sets the base address of the area used for CAR.
@ -177,6 +187,7 @@ config CARSIZE
default 0x8000 if CPU_AMD_GEODELX default 0x8000 if CPU_AMD_GEODELX
default 0x8000 if CPU_AMD_K8 default 0x8000 if CPU_AMD_K8
default 0x8000 if CPU_VIA_C7 default 0x8000 if CPU_VIA_C7
default 0x8000 if CPU_INTEL_CORE2
help help
This option sets the size of the area used for CAR. This option sets the size of the area used for CAR.
@ -186,6 +197,7 @@ config CBMEMK
default 0x1000 if CPU_AMD_GEODELX default 0x1000 if CPU_AMD_GEODELX
default 0x2000 if CPU_AMD_K8 default 0x2000 if CPU_AMD_K8
default 0x1000 if CPU_VIA_C7 default 0x1000 if CPU_VIA_C7
default 0x1000 if CPU_INTEL_CORE2
help help
This option sets the top of the memory area, in KiB, This option sets the top of the memory area, in KiB,
used for coreboot. used for coreboot.

6
mainboard/Kconfig
View file

@ -58,6 +58,11 @@ config VENDOR_JETWAY
help help
Select this option for systems from Jetway. Select this option for systems from Jetway.
config VENDOR_KONTRON
bool "Kontron"
help
Select this option for systems from Kontron.
config VENDOR_EMULATION config VENDOR_EMULATION
bool "Emulated systems" bool "Emulated systems"
help help
@ -82,6 +87,7 @@ source "mainboard/artecgroup/Kconfig"
source "mainboard/emulation/Kconfig" source "mainboard/emulation/Kconfig"
source "mainboard/gigabyte/Kconfig" source "mainboard/gigabyte/Kconfig"
source "mainboard/jetway/Kconfig" source "mainboard/jetway/Kconfig"
source "mainboard/kontron/Kconfig"
source "mainboard/pcengines/Kconfig" source "mainboard/pcengines/Kconfig"
source "mainboard/via/Kconfig" source "mainboard/via/Kconfig"

2
southbridge/intel/i82801gx/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y) ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c