From 4e0cd97c537d6dbc0e1e087ecf6499abfd23e2f4 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 3 May 2017 10:14:07 -0700 Subject: [PATCH] UPSTREAM: mb/google/eve: Set SUSWARN# pin to native function Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied to SUSACK# in the schematic and and is intented to be used in Deep Sx so it should not be configured for GPIO mode. BUG=b:35581264 TEST=build and boot on Eve platform, test that Deep S3 and Deep S5 are still functional. (this change should have no visible effect) Change-Id: I66e41615c4a19083b8bc5835f1139e8f15cd372b Signed-off-by: Patrick Georgi Original-Commit-Id: 1a51086815c099127ec4253e9785b664f2c933f4 Original-Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://review.coreboot.org/19549 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/496049 Commit-Ready: Duncan Laurie --- src/mainboard/google/eve/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 6da82441bd..ed0d7126a0 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -58,7 +58,7 @@ static const struct pad_config gpio_table[] = { /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ /* BM_BUSY# */ PAD_CFG_NC(GPP_A12), -/* SUSWARN# */ PAD_CFG_NC(GPP_A13), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),