Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix for e7501 raminit w/ 533 MHz FSB CPUs

Browse source
This commit is contained in:
Steven James 2003-05-12 13:17:01 +00:00
parent d82a091f36
commit 4b49f27764
1 changed files with 6 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/northbridge/intel/E7501/raminit.inc
View file

@ -197,11 +197,12 @@ constant_register_values:
#if CAS_LATENCY == CAS_2_5
# .long 0x80, 0xfffffe00, 0x06 /* Intel E7500 recommended */
# .long 0x80, 0xfffff000, 0x0bb6 /* Intel E7500 recommended */
.long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
# .long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
.long 0x80, 0xfffff000, 0x0bb1 /* values for register 0x80 */
#elif CAS_LATENCY == CAS_2_0
# .long 0x80, 0xfffffe00, 0x0d /* values for register 0x80 */
# .long 0x80, 0xfffff000, 0x0bb1 /* values for register 0x80 */
.long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
.long 0x80, 0xfffff000, 0x0bb1 /* values for register 0x80 */
# .long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
#elif CAS_LATENCY == CAS_1_5
# .long 0x80, 0xfffffe00, 0x05
# .long 0x80, 0xfffff000, 0x0bb5
@ -1388,7 +1389,8 @@ cas_latency_80:
# .byte 0x05, 0x01, 0x06
# .byte 0xb5, 0xb1, 0xb6
.byte 0x62, 0x62, 0x62 /* factory setting for 0 undocumented reg tnz */
# .byte 0x62, 0x62, 0x62 /* factory setting for 0 undocumented reg tnz */
.byte 0xb1, 0xb1, 0xb1 /* factory setting for 0 undocumented reg tnz */
cas_latency_78:
.byte DRT_CAS_1_5, DRT_CAS_2_0, DRT_CAS_2_5