mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Working -g2 variant of the p4dpe
This commit is contained in:
Ronald G. Minnich
parent
e5b78d984e
commit
4b47dd0ea1
8 changed files with 869 additions and 0 deletions
261
src/mainboard/supermicro/p4dpe/g2/Config
Normal file
261
src/mainboard/supermicro/p4dpe/g2/Config
Normal file
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@ -0,0 +1,261 @@
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## Set all of the defaults for an x86 architecture
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##
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arch i386
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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ldscript cpu/i386/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE
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ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE
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ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript arch/i386/lib/id.lds
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## This is the early phase of linuxBIOS startup
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## Things are delicate and we test to see if we should
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## failover to another image.
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mainboardinit northbridge/intel/E7500/reset_test.inc
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mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE
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mainboardinit southbridge/intel/82801ca/cmos_failover.inc USE_FALLBACK_IMAGE
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ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/i786/earlymtrr.inc
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##
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## Setup the serial port
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##
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mainboardinit superio/winbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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mainboardinit southbridge/intel/82801ca/watchdog_disable.inc
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##
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## Reset pci clock for hardware bug work around
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##
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mainboardinit southbridge/intel/82801ca/smbus.inc
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mainboardinit southbridge/intel/82801ca/smbus_write_block.inc
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mainboardinit mainboard/supermicro/p4dpe/pci_clk_reset.inc
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##
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## Smbus functions
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##
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mainboardinit southbridge/intel/82801ca/smbus_read_byte.inc
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#mainboardinit southbridge/intel/82801ca/smbus_read_block.inc
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#mainboardinit southbridge/intel/82801ca/smbus_print_block.inc
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mainboardinit mainboard/supermicro/p4dpe/select_i2c_spd.inc
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##
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## Setup RAM
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##
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#mainboardinit ram/dump_northbridge.inc
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#mainboardinit sdram/generic_dump_smbus.inc
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#mainboardinit sdram/generic_dump_spd.inc
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mainboardinit mainboard/supermicro/p4dpe/mainboard_raminit.inc
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##
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## Include the secondary Configuration files
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##
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northbridge intel/E7500
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southbridge intel/82801ca
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southbridge intel/82870
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nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 hwmonitor=1
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dir /src/pc80
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dir /src/superio/winbond/w83627hf
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dir /src/ram/
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cpu p5
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cpu p6
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cpu i786
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##
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## Build the objects we have code for in this directory.
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##
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object mainboard.o
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#object devices.o
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object mptable.o HAVE_MP_TABLE
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object irq_tables.o HAVE_PIRQ_TABLE
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###
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### Build options
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###
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##
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## Location of the DIMM EEPROMS on the SMBUS
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## This is fixed into a narrow range by the DIMM package standard.
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##
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option SMBUS_MEM_DEVICE_START=(0xa << 3)
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option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3)
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option SMBUS_MEM_DEVICE_INC=1
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option SMBUS_MEM_CHANNEL_OFF=4
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##
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## Customize our winbond superio chip for this motherboard
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##
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option SIO_BASE=0x2e
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option SIO_SYSTEM_CLK_INPUT=SIO_SYSTEM_CLK_INPUT_48MHZ
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##
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## Build code for the fallback boot
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##
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option HAVE_FALLBACK_BOOT=1
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##
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## Build code for using cache as RAM
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##
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#option USE_CACHE_RAM=0
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##
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## Delay timer options
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##
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option CONFIG_UDELAY_TSC=1
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option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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option HAVE_PIRQ_TABLE=1
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##
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## Do not build special code to the keyboard
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##
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option NO_KEYBOARD=1
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option tabe table
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##
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option HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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option SMP=1
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option MAX_CPUS=4
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option MAX_PHYSICAL_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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option IOAPIC=1
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##
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## MEMORY_HOLE instructs earlymtrr.inc to
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## enable caching from 0-640KB and to disable
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## caching from 640KB-1MB using fixed MTRRs
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##
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## Enabling this option breaks SMP because secondary
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## CPU identification depends on only variable MTRRs
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## being enabled.
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##
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nooption MEMORY_HOLE
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##
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## Figure out which type of linuxBIOS image to build
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## If we aren't a fallback image we must be a normal image
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## This is useful for optional includes
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##
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option USE_FALLBACK_IMAGE=0
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expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE
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###
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### LinuxBIOS layout values
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###
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE=524288
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=49152
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00008000
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## For the trick of using cache as ram
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## put the fake ram location at this address
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option CACHE_RAM_BASE=0xfff70000
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option CACHE_RAM_SIZE=0x00010000
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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##
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## Use a small 8K heap
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##
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option HEAP_SIZE=0x2000
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER=P4DP6
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option MAINBOARD_VENDOR=Supermicro
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option UPDATE_MICROCODE=1
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option CPU_FIXUP=1
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##
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## Only use the option table in a normal image
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##
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expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE - 65536))
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expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE*0)
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE
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##
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## Compute a range of ROM that can cached to speed of linuxBIOS,
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## execution speed.
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##
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expr XIP_ROM_SIZE = 65536
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expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
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27
src/mainboard/supermicro/p4dpe/g2/STATUS
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27
src/mainboard/supermicro/p4dpe/g2/STATUS
Normal file
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@ -0,0 +1,27 @@
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# These are keyword-value pairs.
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# a : separates the keyword from the value
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# the value is arbitrary text delimited by newline.
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# continuation, if needed, will be via the \ at the end of a line
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# comments are indicated by a '#' as the first character.
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# the keywords are case-INSENSITIVE
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owner: Ron Minnich
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email: rminnich@lanl.gov
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#status: One of unsupported, unstable, stable
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status: stable
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explanation:
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flash-types: Intel 82801CA
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payload-types:
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# e.g. linux, plan 9, wince, etc.
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OS-types: Linux
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# e.g. "Plan 9 interrupts don't work on this chipset"
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OS-issues:
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console-types:serial
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# vga is unsupported, unstable, or stable
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vga:unsupported
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# Last-known-good follows the internationl date standard: day/month/year
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last-known-good: 07/02/2003
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Comments:
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Links:
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Mainboard-revision:
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# What other mainboards are like this one? List them here.
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AKA:
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94
src/mainboard/supermicro/p4dpe/g2/cmos.layout
Normal file
94
src/mainboard/supermicro/p4dpe/g2/cmos.layout
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@ -0,0 +1,94 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 2 hyper_threading
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396 1 e 1 thermal_monitoring
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397 1 e 1 remap_memory_high
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400 1 e 1 power_on_after_fail
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#402 1 e 2 hda_disk
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#403 1 e 2 hdb_disk
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#404 1 e 2 hdc_disk
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#405 1 e 2 hdd_disk
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#408 4 e 9 CPU_clock_speed
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 FallBack
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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#9 15 800MHZ
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#9 11 900MHZ
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#9 13 1GHZ
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#9 9 1.1GHZ
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#9 14 1.2GHZ
|
||||
#9 10 1.3GHZ
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#9 12 1.4GHZ
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#9 8 1.5GHZ
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||||
#9 7 1.6GHZ
|
||||
#9 3 1.7GHZ
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||||
#9 5 1.8GHZ
|
||||
#9 1 1.9GHZ
|
||||
#9 6 2.0GHZ
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||||
#9 2 2.1GHZ
|
||||
#9 4 2.2GHZ
|
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#9 0 2.3GHZ
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checksums
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checksum 392 1007 1008
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104
src/mainboard/supermicro/p4dpe/g2/example-fallback.config
Normal file
104
src/mainboard/supermicro/p4dpe/g2/example-fallback.config
Normal file
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## This will make a target directory of ./fallback
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## This is relative to where the configuration file resides in the filesystem
|
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target ./p4dpe-g2-fallback
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mainboard supermicro/p4dpe/g2
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||||
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## Build a fallback not a normal image.
|
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option USE_FALLBACK_IMAGE=1
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||||
## Build an image for a 512KB rom
|
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## ./fallback/romimage is just the last 64KB which we reserve for the fallback image.
|
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option ROM_SIZE=524288
|
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#option ROM_SIZE=1048576
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||||
|
||||
## Select the maximum size the linuxBIOS code can compile to.
|
||||
## Allow linuxBIOS to be up to 48KB in size
|
||||
option ROM_IMAGE_SIZE=40960
|
||||
|
||||
|
||||
##
|
||||
### The Serial Console
|
||||
##
|
||||
## Hardware flow control is currently ignored.
|
||||
|
||||
## Enable the Serial Console
|
||||
option SERIAL_CONSOLE=1
|
||||
|
||||
## Select the serial console baud rate.
|
||||
option TTYS0_BAUD=115200
|
||||
#option TTYS0_BAUD=57600
|
||||
#option TTYS0_BAUD=38400
|
||||
#option TTYS0_BAUD=19200
|
||||
#option TTYS0_BAUD=9600
|
||||
#option TTYS0_BAUD=4800
|
||||
#option TTYS0_BAUD=2400
|
||||
#option TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
option TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
option TTYS0_LCS=0x3
|
||||
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
## At a maximum only compile in this level of debugging
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=4
|
||||
|
||||
## Use the elf bootloader
|
||||
option USE_ELF_BOOT=1
|
||||
|
||||
## Select the boot device
|
||||
option USE_GENERIC_ROM=1
|
||||
#option BOOT_FLOPPY=1
|
||||
#option USE_SERIAL_FILL_INBUF=1
|
||||
#option BOOT_IDE=1
|
||||
|
||||
# Load etherboot with the elf bootloader
|
||||
# The payload command is relative the build directory
|
||||
# So .. is the directory this config file resides in
|
||||
payload ../lnxieepro100.ebi
|
||||
|
||||
|
||||
##
|
||||
## Cpu Speed
|
||||
##
|
||||
option CPU_CLOCK_MULTIPLIER=XEON_X8
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X9
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X10
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X11
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X12
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X13
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X14
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X15
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X16
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X17
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X18
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X19
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X19
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X20
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X21
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X22
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X23
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
|
||||
#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
|
||||
|
||||
105
src/mainboard/supermicro/p4dpe/g2/example-normal.config
Normal file
105
src/mainboard/supermicro/p4dpe/g2/example-normal.config
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
## This will make a target directory of ./normal
|
||||
## This is relative to where the configuration file resides in the filesystem
|
||||
target ./p4dpe-g2-normal
|
||||
|
||||
mainboard supermicro/p4dpe/g2
|
||||
|
||||
## Build a normal not a fallback image.
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
|
||||
## Build an image for a 512KB rom
|
||||
## ./normal/romimage is the entire rom image except for the last 64KB
|
||||
## which are reserved for the fallback image.
|
||||
option ROM_SIZE=524288
|
||||
#option ROM_SIZE=1048576
|
||||
|
||||
## Select the maximum size the linuxBIOS code can compile to.
|
||||
## Allow linuxBIOS to be up to 48KB in size
|
||||
option ROM_IMAGE_SIZE=49152
|
||||
|
||||
|
||||
##
|
||||
### The Serial Console
|
||||
##
|
||||
## Hardware flow control is currently ignored.
|
||||
|
||||
## Enable the Serial Console
|
||||
option SERIAL_CONSOLE=1
|
||||
|
||||
## Select the serial console baud rate.
|
||||
option TTYS0_BAUD=115200
|
||||
#option TTYS0_BAUD=57600
|
||||
#option TTYS0_BAUD=38400
|
||||
#option TTYS0_BAUD=19200
|
||||
#option TTYS0_BAUD=9600
|
||||
#option TTYS0_BAUD=4800
|
||||
#option TTYS0_BAUD=2400
|
||||
#option TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
option TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
option TTYS0_LCS=0x3
|
||||
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
## At a maximum only compile in this level of debugging
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
## Use the elf bootloader
|
||||
option USE_ELF_BOOT=1
|
||||
|
||||
## Select the boot device
|
||||
option USE_GENERIC_ROM=1
|
||||
#option BOOT_FLOPPY=1
|
||||
#option USE_SERIAL_FILL_INBUF=1
|
||||
#option BOOT_IDE=1
|
||||
|
||||
# Load etherboot with the elf bootloader
|
||||
# The payload command is relative the build directory
|
||||
# So .. is the directory this config file resides in
|
||||
payload ../lnxieepro100.ebi
|
||||
|
||||
|
||||
##
|
||||
## Cpu Speed
|
||||
##
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X8
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X9
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X10
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X11
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X12
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X13
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X14
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X15
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X16
|
||||
option CPU_CLOCK_MULTIPLIER=XEON_X17
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X18
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X19
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X19
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X20
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X21
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X22
|
||||
#option CPU_CLOCK_MULTIPLIER=XEON_X23
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
|
||||
#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
|
||||
|
||||
53
src/mainboard/supermicro/p4dpe/g2/irq_tables.c
Normal file
53
src/mainboard/supermicro/p4dpe/g2/irq_tables.c
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*29, /* there can be total 29 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0xf8, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x8086, /* Vendor */
|
||||
0x122e, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x19, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{0,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0x10, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x1,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x2,0x8, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x6, 0},
|
||||
{0x2,0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x7, 0},
|
||||
{0x1,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x3,0x8, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x5, 0},
|
||||
{0x3,0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0xb, 0},
|
||||
{0,0x18, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x5,0x8, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x3, 0},
|
||||
{0x5,0x10, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x2, 0},
|
||||
{0x5,0x18, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x1, 0},
|
||||
{0x4,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x6,0x8, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x4, 0},
|
||||
{0x6,0x10, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x9, 0},
|
||||
{0,0x20, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x10,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x11,0x8, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x8, 0},
|
||||
{0x10,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x12,0x8, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x7, 0},
|
||||
{0,0xf0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x7,0x8, {{0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}}, 0xa, 0},
|
||||
{0x7,0x10, {{0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}}, 0xb, 0},
|
||||
{0x7,0x18, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0xc, 0},
|
||||
{0,0xe8, {{0x60, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xe9, {{0, 0xdef8}, {0x63, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xea, {{0, 0xdef8}, {0, 0xdef8}, {0x62, 0xdcb8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xf8, {{0x62, 0xdcb8}, {0x61, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
}
|
||||
};
|
||||
110
src/mainboard/supermicro/p4dpe/g2/mainboard.c
Normal file
110
src/mainboard/supermicro/p4dpe/g2/mainboard.c
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
#include <arch/io.h>
|
||||
#include <part/mainboard.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <southbridge/intel/82801.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <pc80/isa_dma.h>
|
||||
#include <cpu/i786/multiplier.h>
|
||||
#include <cpu/i786/thermal_monitoring.h>
|
||||
#include <cpu/p6/msr.h>
|
||||
#include <superio/w83627hf.h>
|
||||
#include <superio/generic.h>
|
||||
#include <subr.h>
|
||||
#include <smbus.h>
|
||||
#include <ramtest.h>
|
||||
#include <northbridge/intel/82860/rdram.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0, 6, 1, 7
|
||||
};
|
||||
|
||||
#ifndef CPU_CLOCK_MULTIPLIER
|
||||
#define CPU_CLOCK_MULTIPLIER XEON_X17
|
||||
#endif
|
||||
|
||||
#define MAINBOARD_POWER_OFF 0
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
|
||||
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
static void set_power_on_after_power_fail(int setting)
|
||||
{
|
||||
switch(setting) {
|
||||
case MAINBOARD_POWER_ON:
|
||||
default:
|
||||
ich3_power_after_power_fail(1);
|
||||
w83627hf_power_after_power_fail(POWER_ON);
|
||||
break;
|
||||
case MAINBOARD_POWER_OFF:
|
||||
ich3_power_after_power_fail(0);
|
||||
w83627hf_power_after_power_fail(POWER_OFF);
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void set_thermal_monitoring(int thermal_monitoring)
|
||||
{
|
||||
int tm_high,tm_low;
|
||||
|
||||
rdmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
if(thermal_monitoring != THERMAL_MONITORING_OFF) {
|
||||
tm_low |= THERMAL_MONITORING_SET;
|
||||
}
|
||||
else {
|
||||
tm_low &= ~THERMAL_MONITORING_SET;
|
||||
}
|
||||
wrmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
return;
|
||||
}
|
||||
|
||||
void mainboard_fixup(void)
|
||||
{
|
||||
int cpu_clock_multiplier;
|
||||
int power_on_after_power_fail;
|
||||
int thermal_monitoring;
|
||||
|
||||
w83627hf_power_led(LED_ON);
|
||||
ich3_enable_ioapic();
|
||||
p64h2_enable_ioapic();
|
||||
p64h2_setup_pcibridge();
|
||||
ich3_enable_serial_irqs();
|
||||
ich3_enable_ide(1,1);
|
||||
ich3_rtc_init();
|
||||
ich3_lpc_route_dma(0xff);
|
||||
isa_dma_init();
|
||||
ich3_1e0_misc();
|
||||
ich3_1f0_misc();
|
||||
|
||||
#if 0 /* CPU clock option is not presently used */
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
if(get_option(&cpu_clock_multiplier, "CPU_clock_speed"))
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
ich3_set_cpu_multiplier(cpu_clock_multiplier);
|
||||
#endif
|
||||
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
if(get_option(&power_on_after_power_fail, "power_on_after_fail"))
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
set_power_on_after_power_fail(power_on_after_power_fail);
|
||||
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
if(get_option(&thermal_monitoring, "thermal_monitoring"))
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
set_thermal_monitoring(thermal_monitoring);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
ich3_hard_reset();
|
||||
}
|
||||
|
||||
115
src/mainboard/supermicro/p4dpe/g2/mptable.c
Normal file
115
src/mainboard/supermicro/p4dpe/g2/mptable.c
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/* generatred by MPTable, version 2.0.15*/
|
||||
/* as modified by RGM for LinuxBIOS */
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <string.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "LNXI ";
|
||||
static const char productid[12] = "P4DPE ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "PCI ");
|
||||
smp_write_bus(mc, 4, "PCI ");
|
||||
smp_write_bus(mc, 5, "PCI ");
|
||||
smp_write_bus(mc, 6, "PCI ");
|
||||
smp_write_bus(mc, 7, "PCI ");
|
||||
smp_write_bus(mc, 8, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 4, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 5, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 8, 0x20, base);
|
||||
}
|
||||
}
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x5, 0x2, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x9, 0x2, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xf, 0x2, 0xf);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x8, 0x3, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x9, 0x3, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x7, 0x4, 0x2, 0x10);
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue