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UPSTREAM: soc/intel/skylake: Add macro for setting GPIO interrupt trigger mode.

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Currently, there is no macro to set GPIO interrupt trigger mode.
The purpose is to make coreboot set same trigger mode as GpioInt

BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume

Change-Id: I3c9b8ac398708d6bde8a41044a77fed8acc8daed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4db78e39da
Original-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19992
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523974
This commit is contained in:
Kane Chen 2017-05-31 18:36:45 +08:00 • committed by chrome-bot
parent abfc59ae4a
commit 4aec5f8931
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/skylake/include/soc/gpio.h
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@ -140,6 +140,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
PAD_FIELD(HOSTSW, GPIO)) PAD_FIELD(HOSTSW, GPIO))
/* General purpose input passed through to GPIO interrupt */
#define PAD_CFG_GPI_INT(pad_, term_, rst_, trig_) \
_PAD_CFG_ATTRS(pad_, term_, \
_DW0_VALS(rst_, RAW, NO, trig_, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
PAD_FIELD(HOSTSW, GPIO))
/* General purpose input passed through to IOxAPIC. Assume APIC logic can /* General purpose input passed through to IOxAPIC. Assume APIC logic can
* handle polarity/edge/level constraints. */ * handle polarity/edge/level constraints. */
#define PAD_CFG_GPI_APIC(pad_, term_, rst_) \ #define PAD_CFG_GPI_APIC(pad_, term_, rst_) \