mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
clean up on Makefiles and MTRR/L2 stuff
This commit is contained in:
Li-Ta Lo
parent
faced47a79
commit
4aec1cf42a
4 changed files with 261 additions and 286 deletions
|
|
@ -1,4 +1,4 @@
|
|||
CPUFLAGS=-DSIS630 -Di386 -Di486 -Di686 -Di586 -D__KERNEL__
|
||||
CPUFLAGS = -DSIS630 -Di386 -Di486 -Di686 -Di586 -D__KERNEL__
|
||||
CPUFLAGS += -DINTEL_BRIDGE_CONFIG -DSIS630_NVRAM
|
||||
CPUFLAGS += -DINTEL_PPRO_MTRR -DSIS630_KEYBOARD
|
||||
# CPUFLAGS += -DMUST_ENABLE_FLOPPY
|
||||
|
|
@ -11,7 +11,7 @@ CPUFLAGS += -DUSE_DOC_MIL
|
|||
CPUFLAGS += -DCMD_LINE='"root=/dev/hda1 single"'
|
||||
CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
|
||||
|
||||
LINUX=$(TOP)/../linux-2.4.0-test6.sis
|
||||
LINUX=$(TOP)/linux-2.4.0-test11-linuxbios
|
||||
|
||||
TOP=../..
|
||||
INCLUDES=-nostdinc -I $(TOP)/src/include
|
||||
|
|
@ -75,47 +75,46 @@ mkrom: $(TOP)/mkrom/mkrom.c
|
|||
cc -o mkrom $<
|
||||
|
||||
linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
mainboard.o: $(TOP)/src/mainboard/leadtek/winfast6300/mainboard.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
params.o: $(TOP)/src/lib/params.c
|
||||
cc $(CFLAGS) $(LINUXINCLUDE) -c $<
|
||||
$(CC) $(LINUXINCLUDE) -c $<
|
||||
|
||||
hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
southbridge.o: $(TOP)/src/northsouthbridge/sis/630/southbridge.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
northbridge.o: $(TOP)/src/northsouthbridge/sis/630/northbridge.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
superio.o: $(TOP)/src/superio/sis/950/superio.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
pci.o: $(TOP)/src/lib/pci.c
|
||||
cc $(CFLAGS) -c $<
|
||||
|
||||
$(CC) -c $<
|
||||
|
||||
irq_tables.o: $(TOP)/src/mainboard/leadtek/winfast6300/irq_tables.c
|
||||
cc $(CFLAGS) -o $@ -c $<
|
||||
$(CC) -o $@ -c $<
|
||||
|
||||
mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
subr.o: $(TOP)/src/lib/subr.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
keyboard.o: $(TOP)/src/pc80/keyboard.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
|
||||
$(CC) $(CFLAGS) -c $<
|
||||
|
|
@ -124,22 +123,24 @@ microcode.o: $(TOP)/src/cpu/p6/microcode.c
|
|||
$(CC) $(CFLAGS) -c $<
|
||||
|
||||
serial_subr.o: $(TOP)/src/lib/serial_subr.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
printk.o: $(TOP)/src/lib/printk.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
vsprintf.o: $(TOP)/src/lib/vsprintf.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
newpci.o: $(TOP)/src/lib/newpci.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
linuxpci.o: $(TOP)/src/lib/linuxpci.c
|
||||
cc $(CFLAGS) -c $<
|
||||
$(CC) -c $<
|
||||
|
||||
# I have noe idea why you can not use $(CPUFLAGS) to compile ipl.S
|
||||
# a bug with -Di686 ??
|
||||
ipl.o: $(TOP)/src/northsouthbridge/sis/630/ipl.S
|
||||
gcc -c -I$(TOP)/northsouthbridge/sis/630 $<
|
||||
gcc -c -DHAVE_FRAMEBUFFER -I$(TOP)/northsouthbridge/sis/630 $<
|
||||
|
||||
vmlinux.bin.gz.block: vmlinux.bin.gz
|
||||
dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
|
||||
|
|
|
|||
|
|
@ -94,10 +94,8 @@ int intel_l2_configure()
|
|||
|
||||
intel_cpuid(0, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
if (ebx != 0x756e6547 ||
|
||||
edx != 0x49656e69 ||
|
||||
ecx != 0x6c65746e)
|
||||
{
|
||||
if (ebx != 0x756e6547 || edx != 0x49656e69 ||
|
||||
ecx != 0x6c65746e) {
|
||||
printk(KERN_ERR "Not 'GenuineIntel' Processor\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -106,14 +104,12 @@ int intel_l2_configure()
|
|||
|
||||
/* Mask out the stepping */
|
||||
signature = eax & 0xfff0;
|
||||
if (signature & 0x1000)
|
||||
{
|
||||
if (signature & 0x1000) {
|
||||
DBG("Overdrive chip no L2 cache configuration\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (signature < 0x630 || signature >= 0x680)
|
||||
{
|
||||
if (signature < 0x630 || signature >= 0x680) {
|
||||
DBG("CPU signature of %x so no need for L2 cache configuration\n",
|
||||
signature);
|
||||
return 0;
|
||||
|
|
@ -121,15 +117,13 @@ int intel_l2_configure()
|
|||
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
/* If bit 23 (L2 Hardware disable is set then done */
|
||||
if (eax & 0x800000)
|
||||
{
|
||||
/* If bit 23 (L2 Hardware disable) is set then done */
|
||||
if (eax & 0x800000) {
|
||||
DBG("L2 Hardware disabled\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (signature == 0x630)
|
||||
{
|
||||
if (signature == 0x630) {
|
||||
/* 0x630 signature setup */
|
||||
|
||||
/* Read EBL_CR_POWERON */
|
||||
|
|
@ -137,8 +131,7 @@ int intel_l2_configure()
|
|||
|
||||
/* Mask out [22-24] Clock frequency ratio */
|
||||
eax &= 0x1c00000;
|
||||
if (eax == 0xc00000 || eax == 0x1000000)
|
||||
{
|
||||
if (eax == 0xc00000 || eax == 0x1000000) {
|
||||
printk(KERN_ERR "Incorrect clock frequency ratio %x\n", eax);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -165,9 +158,7 @@ int intel_l2_configure()
|
|||
eax |= 0x44000;
|
||||
/* Write BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
int calc_eax;
|
||||
int v;
|
||||
|
||||
|
|
@ -178,8 +169,7 @@ int intel_l2_configure()
|
|||
|
||||
/* Mask out [22-24] Clock frequency ratio */
|
||||
eax &= 0x3c00000;
|
||||
if (eax == 0xc00000 || eax == 0x3000000)
|
||||
{
|
||||
if (eax == 0xc00000 || eax == 0x3000000) {
|
||||
printk(KERN_ERR "Incorrect clock frequency ratio %x\n", eax);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -234,15 +224,13 @@ int intel_l2_configure()
|
|||
|
||||
/* Read L2 register 0 */
|
||||
tmp = read_l2(0);
|
||||
if (tmp < 0)
|
||||
{
|
||||
if (tmp < 0) {
|
||||
printk(KERN_ERR "Failed to read_l2(0)\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* test if L2(0) has bit 0x20 set */
|
||||
if ((tmp & 0x20) != 0)
|
||||
{
|
||||
if ((tmp & 0x20) != 0) {
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
/* Set bits [6-7] CRTN + Address Parity enable */
|
||||
|
|
@ -251,20 +239,17 @@ int intel_l2_configure()
|
|||
wrmsr(0x11e, eax, edx);
|
||||
}
|
||||
|
||||
if (calculate_l2_ecc() != 0)
|
||||
{
|
||||
if (calculate_l2_ecc() != 0) {
|
||||
printk(KERN_ERR "Failed to calculate L2 ECC\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (calculate_l2_physical_address_range() != 0)
|
||||
{
|
||||
if (calculate_l2_physical_address_range() != 0) {
|
||||
printk(KERN_ERR "Failed to calculate L2 physical address range\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (calculate_l2_cache_size() != 0)
|
||||
{
|
||||
if (calculate_l2_cache_size() != 0) {
|
||||
printk(KERN_ERR "Failed to calculate L2 cache size\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -283,21 +268,18 @@ int intel_l2_configure()
|
|||
DBG("L2 Cache size is %dK\n", cache_size*4/1024);
|
||||
|
||||
/* Write to all cache lines to initialize */
|
||||
while(cache_size > 0)
|
||||
{
|
||||
while(cache_size > 0) {
|
||||
int way;
|
||||
|
||||
/* Each Cache line in 32 bytes */
|
||||
cache_size -= 0x20;
|
||||
|
||||
/* Update each way */
|
||||
for(way = 0; way < 4; way++)
|
||||
{
|
||||
for(way = 0; way < 4; way++) {
|
||||
/* Send Tag Write w/Data Write (TWW) to L2 controller
|
||||
* MESI = Invalid
|
||||
*/
|
||||
if (signal_l2(0, cache_size, 0, 0, way, 0x1c) != 0)
|
||||
{
|
||||
if (signal_l2(0, cache_size, 0, 0, way, 0x1c) != 0) {
|
||||
printk(KERN_ERR "Failed on signal_l2(%x, %x)\n",
|
||||
cache_size, way);
|
||||
return -1;
|
||||
|
|
|
|||
|
|
@ -115,14 +115,11 @@ void intel_set_fixed_mtrr()
|
|||
high = *(unsigned long *) fixed_mtrr_values[i*2+1];
|
||||
wrmsr(mtrr_msr[i], low, high);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* setting variable mtrr, comes from linux kernel source */
|
||||
void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
|
||||
{
|
||||
|
||||
|
||||
if (reg >= 8)
|
||||
return;
|
||||
|
||||
|
|
@ -136,17 +133,6 @@ void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size
|
|||
}
|
||||
}
|
||||
|
||||
/* some secret MSR registers make 5x performance boost,
|
||||
hardcoded for 128MB SDRAM on Celeron and PII */
|
||||
void intel_l2_cache_on()
|
||||
{
|
||||
unsigned long low, high;
|
||||
|
||||
low = 0x134052b;
|
||||
high = 0x00;
|
||||
wrmsr(0x11e, low, high);
|
||||
}
|
||||
|
||||
/* setting up variable and fixed mtrr
|
||||
ToDo: 1. still need to find out how to set size and alignment correctly
|
||||
2. should we invalid cache by INVLD or WBINVD ?? */
|
||||
|
|
@ -169,7 +155,7 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
|||
printk(KERN_INFO "set_mtrr: rambase is 0x%x, ramsizeK is 0x%x\n",
|
||||
rambase, ramsizeK);
|
||||
#if 0
|
||||
// why doesn't this work! machine hangs!
|
||||
// why doesn't this work! machine hangs!
|
||||
printk(KERN_INFO "setting MTRR 0 size to 0x%x\n",
|
||||
(ramsizeK + 4096) * 1024);
|
||||
intel_set_var_mtrr(0, 0, (ramsizeK + 4096) * 1024, MTRR_TYPE_WRBACK);
|
||||
|
|
@ -178,7 +164,9 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
|||
#else
|
||||
// Ollie, this is a hack! Sorry! Ron
|
||||
printk(KERN_INFO "Setting 256M MTRR 0\n");
|
||||
intel_set_var_mtrr(0, 0, 256 * 1024 * 1024, MTRR_TYPE_WRBACK);
|
||||
intel_set_var_mtrr(0, 0, 128 * 1024 * 1024, MTRR_TYPE_WRBACK);
|
||||
intel_set_var_mtrr(1, 124 *1024 * 1024, 4096 * 1024, MTRR_TYPE_UNCACHABLE);
|
||||
|
||||
#ifdef HAVE_FRAMEBUFFER
|
||||
// for SiS, ramsizeK is the base of the framebuffer.
|
||||
// but if it's less than 60M, don't bother ...
|
||||
|
|
@ -186,23 +174,24 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
|||
{
|
||||
printk(KERN_INFO "Setting %dM, 4M size MTRR 1\n",
|
||||
ramsizeK);
|
||||
intel_set_var_mtrr(1, ramsizeK * 1024, 4096 * 1024,
|
||||
MTRR_TYPE_UNCACHABLE);
|
||||
// intel_set_var_mtrr(1, ramsizeK * 1024, 4096 * 1024,
|
||||
// MTRR_TYPE_UNCACHABLE);
|
||||
}
|
||||
#endif
|
||||
#endif /* HAVE_FRAMEBUFFER*/
|
||||
|
||||
printk(KERN_INFO "MTRRs set\n");
|
||||
#endif
|
||||
#else
|
||||
|
||||
#else /* SIS630 */
|
||||
printk("Setting variable MTRR 0 to %dK\n", ramsizeK);
|
||||
intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK);
|
||||
#endif
|
||||
#endif /* SIS630 */
|
||||
|
||||
intel_set_fixed_mtrr();
|
||||
|
||||
/* enable fixed MTRR */
|
||||
intel_enable_fixed_mtrr();
|
||||
intel_enable_var_mtrr();
|
||||
|
||||
//intel_l2_cache_on();
|
||||
}
|
||||
#else /* ENABLE_FIXED_AND_VARIABLE_MTRRS */
|
||||
void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
|
||||
|
|
|
|||
|
|
@ -166,15 +166,18 @@ no_sdram:
|
|||
movb $0x63, %ah
|
||||
#ifdef HAVE_FRAMEBUFFER
|
||||
orb $0x90, %al # enable SMA 4 MB for VGA
|
||||
#endif
|
||||
#else /* SIZE_ALL */
|
||||
#endif /* HAVE_FRAMEBUFFER */
|
||||
|
||||
#else /* !SIZE_ALL */
|
||||
|
||||
no_sdram:
|
||||
#ifdef HAVE_FRAMEBUFFER
|
||||
# enable DIMM 0 and
|
||||
movw $0x6391, %ax # enable SMA 4 MB for VGA
|
||||
#else
|
||||
#else /* HAVE_FRAMEBUFFER */
|
||||
movw $0x6301, %ax # enable DIMM 0
|
||||
#endif // HAVE_FRAMEBUFFER
|
||||
#endif /* HAVE_FRAMEBUFFER */
|
||||
|
||||
#endif /* SIZE_ALL */
|
||||
|
||||
CALL_SP(write_pci_register) # write register 0x63
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue