mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
clean up on Makefiles and MTRR/L2 stuff
This commit is contained in:
Li-Ta Lo
parent
faced47a79
commit
4aec1cf42a
4 changed files with 261 additions and 286 deletions
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@ -11,7 +11,7 @@ CPUFLAGS += -DUSE_DOC_MIL
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CPUFLAGS += -DCMD_LINE='"root=/dev/hda1 single"'
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CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
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LINUX=$(TOP)/../linux-2.4.0-test6.sis
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LINUX=$(TOP)/linux-2.4.0-test11-linuxbios
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TOP=../..
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INCLUDES=-nostdinc -I $(TOP)/src/include
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@ -75,47 +75,46 @@ mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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mainboard.o: $(TOP)/src/mainboard/leadtek/winfast6300/mainboard.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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params.o: $(TOP)/src/lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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$(CC) $(LINUXINCLUDE) -c $<
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hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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southbridge.o: $(TOP)/src/northsouthbridge/sis/630/southbridge.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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northbridge.o: $(TOP)/src/northsouthbridge/sis/630/northbridge.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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superio.o: $(TOP)/src/superio/sis/950/superio.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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pci.o: $(TOP)/src/lib/pci.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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irq_tables.o: $(TOP)/src/mainboard/leadtek/winfast6300/irq_tables.c
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cc $(CFLAGS) -o $@ -c $<
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$(CC) -o $@ -c $<
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mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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subr.o: $(TOP)/src/lib/subr.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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keyboard.o: $(TOP)/src/pc80/keyboard.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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$(CC) $(CFLAGS) -c $<
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@ -124,22 +123,24 @@ microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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vsprintf.o: $(TOP)/src/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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newpci.o: $(TOP)/src/lib/newpci.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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linuxpci.o: $(TOP)/src/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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$(CC) -c $<
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# I have noe idea why you can not use $(CPUFLAGS) to compile ipl.S
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# a bug with -Di686 ??
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ipl.o: $(TOP)/src/northsouthbridge/sis/630/ipl.S
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gcc -c -I$(TOP)/northsouthbridge/sis/630 $<
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gcc -c -DHAVE_FRAMEBUFFER -I$(TOP)/northsouthbridge/sis/630 $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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@ -94,10 +94,8 @@ int intel_l2_configure()
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intel_cpuid(0, &eax, &ebx, &ecx, &edx);
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if (ebx != 0x756e6547 ||
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edx != 0x49656e69 ||
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ecx != 0x6c65746e)
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{
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if (ebx != 0x756e6547 || edx != 0x49656e69 ||
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ecx != 0x6c65746e) {
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printk(KERN_ERR "Not 'GenuineIntel' Processor\n");
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return -1;
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}
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@ -106,14 +104,12 @@ int intel_l2_configure()
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/* Mask out the stepping */
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signature = eax & 0xfff0;
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if (signature & 0x1000)
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{
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if (signature & 0x1000) {
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DBG("Overdrive chip no L2 cache configuration\n");
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return 0;
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}
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if (signature < 0x630 || signature >= 0x680)
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{
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if (signature < 0x630 || signature >= 0x680) {
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DBG("CPU signature of %x so no need for L2 cache configuration\n",
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signature);
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return 0;
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@ -121,15 +117,13 @@ int intel_l2_configure()
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/* Read BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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/* If bit 23 (L2 Hardware disable is set then done */
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if (eax & 0x800000)
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{
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/* If bit 23 (L2 Hardware disable) is set then done */
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if (eax & 0x800000) {
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DBG("L2 Hardware disabled\n");
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return 0;
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}
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if (signature == 0x630)
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{
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if (signature == 0x630) {
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/* 0x630 signature setup */
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/* Read EBL_CR_POWERON */
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@ -137,8 +131,7 @@ int intel_l2_configure()
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/* Mask out [22-24] Clock frequency ratio */
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eax &= 0x1c00000;
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if (eax == 0xc00000 || eax == 0x1000000)
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{
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if (eax == 0xc00000 || eax == 0x1000000) {
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printk(KERN_ERR "Incorrect clock frequency ratio %x\n", eax);
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return -1;
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}
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@ -165,9 +158,7 @@ int intel_l2_configure()
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eax |= 0x44000;
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/* Write BBL_CR_CTL3 */
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wrmsr(0x11e, eax, edx);
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}
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else
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{
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} else {
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int calc_eax;
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int v;
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@ -178,8 +169,7 @@ int intel_l2_configure()
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/* Mask out [22-24] Clock frequency ratio */
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eax &= 0x3c00000;
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if (eax == 0xc00000 || eax == 0x3000000)
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{
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if (eax == 0xc00000 || eax == 0x3000000) {
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printk(KERN_ERR "Incorrect clock frequency ratio %x\n", eax);
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return -1;
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}
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@ -234,15 +224,13 @@ int intel_l2_configure()
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/* Read L2 register 0 */
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tmp = read_l2(0);
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if (tmp < 0)
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{
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if (tmp < 0) {
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printk(KERN_ERR "Failed to read_l2(0)\n");
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return -1;
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}
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/* test if L2(0) has bit 0x20 set */
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if ((tmp & 0x20) != 0)
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{
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if ((tmp & 0x20) != 0) {
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/* Read BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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/* Set bits [6-7] CRTN + Address Parity enable */
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@ -251,20 +239,17 @@ int intel_l2_configure()
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wrmsr(0x11e, eax, edx);
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}
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if (calculate_l2_ecc() != 0)
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{
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if (calculate_l2_ecc() != 0) {
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printk(KERN_ERR "Failed to calculate L2 ECC\n");
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return -1;
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}
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if (calculate_l2_physical_address_range() != 0)
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{
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if (calculate_l2_physical_address_range() != 0) {
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printk(KERN_ERR "Failed to calculate L2 physical address range\n");
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return -1;
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}
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if (calculate_l2_cache_size() != 0)
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{
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if (calculate_l2_cache_size() != 0) {
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printk(KERN_ERR "Failed to calculate L2 cache size\n");
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return -1;
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}
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@ -283,21 +268,18 @@ int intel_l2_configure()
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DBG("L2 Cache size is %dK\n", cache_size*4/1024);
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/* Write to all cache lines to initialize */
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while(cache_size > 0)
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{
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while(cache_size > 0) {
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int way;
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/* Each Cache line in 32 bytes */
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cache_size -= 0x20;
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/* Update each way */
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for(way = 0; way < 4; way++)
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{
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for(way = 0; way < 4; way++) {
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/* Send Tag Write w/Data Write (TWW) to L2 controller
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* MESI = Invalid
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*/
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if (signal_l2(0, cache_size, 0, 0, way, 0x1c) != 0)
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{
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if (signal_l2(0, cache_size, 0, 0, way, 0x1c) != 0) {
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printk(KERN_ERR "Failed on signal_l2(%x, %x)\n",
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cache_size, way);
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return -1;
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@ -115,14 +115,11 @@ void intel_set_fixed_mtrr()
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high = *(unsigned long *) fixed_mtrr_values[i*2+1];
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wrmsr(mtrr_msr[i], low, high);
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}
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}
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/* setting variable mtrr, comes from linux kernel source */
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void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
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{
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if (reg >= 8)
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return;
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@ -136,17 +133,6 @@ void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size
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}
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}
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/* some secret MSR registers make 5x performance boost,
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hardcoded for 128MB SDRAM on Celeron and PII */
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void intel_l2_cache_on()
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{
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unsigned long low, high;
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low = 0x134052b;
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high = 0x00;
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wrmsr(0x11e, low, high);
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}
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/* setting up variable and fixed mtrr
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ToDo: 1. still need to find out how to set size and alignment correctly
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2. should we invalid cache by INVLD or WBINVD ?? */
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@ -178,7 +164,9 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
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#else
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// Ollie, this is a hack! Sorry! Ron
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printk(KERN_INFO "Setting 256M MTRR 0\n");
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intel_set_var_mtrr(0, 0, 256 * 1024 * 1024, MTRR_TYPE_WRBACK);
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intel_set_var_mtrr(0, 0, 128 * 1024 * 1024, MTRR_TYPE_WRBACK);
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intel_set_var_mtrr(1, 124 *1024 * 1024, 4096 * 1024, MTRR_TYPE_UNCACHABLE);
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#ifdef HAVE_FRAMEBUFFER
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// for SiS, ramsizeK is the base of the framebuffer.
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// but if it's less than 60M, don't bother ...
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@ -186,23 +174,24 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
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{
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printk(KERN_INFO "Setting %dM, 4M size MTRR 1\n",
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ramsizeK);
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intel_set_var_mtrr(1, ramsizeK * 1024, 4096 * 1024,
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MTRR_TYPE_UNCACHABLE);
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// intel_set_var_mtrr(1, ramsizeK * 1024, 4096 * 1024,
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// MTRR_TYPE_UNCACHABLE);
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}
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#endif
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#endif /* HAVE_FRAMEBUFFER*/
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printk(KERN_INFO "MTRRs set\n");
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#endif
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#else
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#else /* SIS630 */
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printk("Setting variable MTRR 0 to %dK\n", ramsizeK);
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intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK);
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#endif
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#endif /* SIS630 */
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intel_set_fixed_mtrr();
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/* enable fixed MTRR */
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intel_enable_fixed_mtrr();
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intel_enable_var_mtrr();
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//intel_l2_cache_on();
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}
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#else /* ENABLE_FIXED_AND_VARIABLE_MTRRS */
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void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
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@ -166,15 +166,18 @@ no_sdram:
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movb $0x63, %ah
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#ifdef HAVE_FRAMEBUFFER
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orb $0x90, %al # enable SMA 4 MB for VGA
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#endif
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#else /* SIZE_ALL */
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#endif /* HAVE_FRAMEBUFFER */
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#else /* !SIZE_ALL */
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no_sdram:
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#ifdef HAVE_FRAMEBUFFER
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# enable DIMM 0 and
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movw $0x6391, %ax # enable SMA 4 MB for VGA
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#else
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#else /* HAVE_FRAMEBUFFER */
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movw $0x6301, %ax # enable DIMM 0
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#endif // HAVE_FRAMEBUFFER
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#endif /* HAVE_FRAMEBUFFER */
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#endif /* SIZE_ALL */
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CALL_SP(write_pci_register) # write register 0x63
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